Minakshisundaran Balasubramanian Anand

NURA: a feasible, gas-dielectric interconnect process

We have proposed a gas-dielectric interconnect process, and demonstrated its feasibility. While several engineering problems need to tackled before the proposed process is manufacturable, the incentive for further development of this process is huge since it can lead to the minimum physical value of the relative dielectric constant, 1.0.

Use of gas as low-k interlayer dielectric in LSI's: Demonstration of feasibility

Reduction of the wire capacitance in LSIs has become an issue of the utmost importance since the wire parasitic capacitance plays a significant role in determining both chip speed and power. Low dielectric constant materials such as SiOF (k=3.3) are already in use in manufacturing, while other materials with lower dielectric constants (k=2.0/spl sim/3.0) are under development. Technology for further reduction of the dielectric constant, however, has not been reported so far. In this paper, we propose a gas-dielectric process that has the potential to achieve almost the minimum physically possible value for the dielectric constant: 1.0. The conceptual feasibility of the process is demonstrated, and basic process characterization data are presented. In addition, issues to be considered when integrating the proposed process into LSI manufacturing are identified, and work currently in progress addressing these issues is discussed.

Multiobjective optimization of VLSI interconnect parameters

The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap. Last, shortcomings of and possible improvements to existing system-level critical path models are discussed.

Low resistance dual damascene process by new Al reflow using Nb liner

Summary form only given. This paper describes excellent Al filling characteristics and low resistance dual damascene interconnects obtained with a new Al reflow process using Nb liner. This novel process can fill vias of AR4 and can achieve 40-50% drop in resistance compared with current RIE-Al lines and reflow-Al lines with Ti liner. These properties are attributed to a slower reaction rate between Nb and Al. Excellent via electrical properties have been verified across 200 mm wafers using this process. This new process is a leading candidate for sub-0.25-0.15 um Al metallization.

A Fully Integrated Aluminum Dual Damascene Process Using a New Double Stopper Structure.

A fully integrated aluminum dual damascene process is presented. The process incorporates a double silicon nitride etch stopper structure to achieve better etching control. Use of silicon nitride etch stoppers usually results in increased wire capacitance. However, the new process presented here succeeds in significantly reducing the impact of the silicon nitride stopper layers on wire capacitance by arranging for the stopper layers to be away from the wire corners. The integration of this process with a previously reported aluminum reflow process to obtain an integrated aluminum dual damascene process is described and the results obtained are discussed.

Optimization study of VLSI interconnect parameters

In this paper, we present the results of optimizing interconnect parameters to satisfy chip-level targets in future device generations. The optimization approach used is based on existing system-level models and can optimize the number of wire levels, speed, chip size, and power in sequence, with the optimization variables being all interconnect parameters such as pitches, thicknesses, etc. We also study the trade-offs resulting from various interconnect process limitations and choices. The findings of this study, in brief, are: 1) while the thickness of the interlayer dielectric (ILD) can be scaled without adverse effects on speed so that the hole aspect ratio is held constant at about 3.0 across generations, it is important to provide extremely thick ILD films in excess of 4 pm in the upper wire levels, 2) while the maximum wire thickness can be safely held to about 2 /spl mu/m in the upper wire levels, extremely thin wires of less than 0.1 pm thickness will soon be needed in the lower wire levels to reduce capacitance, 3) while wire resistivity reduction is desirable it is much more important to reduce the ILD dielectric constant aggressively, and 4) chip size constraints can impact the speed extremely and need to considered carefully. These results can be used to construct an optimal interconnect technology roadmap and can be an invaluable aid in guiding interconnect process development.

A STUDY OF MECHANICAL STABILITY ISSUES IN MULTILEVEL AIR-DIELECTRIC INTERCONNECT SCHEMES FOR ULSIS

Air-dielectric interconnect schemes are under active consideration for use in high performance LSIs because they can improve speed significantly. However, mechanical stability is the biggest engineering issue in these schemes. In this paper, an investigation of mechanical stability issues is presented. It is found that the deflection of the wires due to their own weight is unlikely to be a problem. For a typical long wire cross-section of 2 µm×2 µm, wires of length slightly more than 1mm can be allowed without appreciable sag. On the other hand, it is found that the initial tensile stress in the metal wires produces significant bending stresses at the bottom of the via plugs. The dependence of the bending stress on various geometrical parameters is studied in detail. It is found that bending stresses of more than 1 GPa can result even for a very low initial tensile stress in the wire of 20 MPa.