Masahiro Inohara

Copper contamination induced degradation of MOSFET characteristics and reliability

MOSFET electrical characteristics and reliability impact with copper contamination is examined and some degradation modes are inspected. The mechanism of degradation is explained by increase of carrier trap sites in gate silicon oxide. The permissive contamination level of copper in device region is indicated by comparison between two different contamination level samples.

Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

Leading-edge LSI products with 40nm logic technology node and beyond are facing the issue of how higher memory bandwidth is reconciled with lower power consumption. Chip stacking of a logic chip on a large-scale DRAM chip, interconnected with each other by fine-pitch bumps, provides a solution to realize a power efficient SiP (System in Package). In this paper, the successful process integration of 10µm pitch Cu redistribution wiring and 40µm pitch SnCu micro-bumping on 300mm wafers, together with chip-on-chip (CoC) joining, has been described in an effort to relinquish embedded DRAM (eDRAM) SoC (System on Chip).

Process and design tradeoffs between minimum RC signal propagation delay and interconnect current density and resistance for deep submicrometer ICs

The demand for higher current density in metal interconnects continues to increase to meet the challenges of higher operation frequency and the more complex design requirement of deep submicrometer integrated circuits. However, improvement in the allowable interconnect current density is typically accompanied by higher wire resistance. The tradeoff between wire resistance and allowable current density must be managed to realize the most efficient interconnect system because both wire resistance and allowable current density affect signal propagation delay. This paper studies the impact of allowable current density on signal propagation delay, and demonstrates an approach to balance wire resistance and allowable current density from the perspective of minimizing signal propagation delay.