Tadashi Matsuno

High performance half-micron PMOSFETs with 0.1um shallow P + N junction utilizing selective silicon growth and rapid thermal annealing

High performance half-micron PMOSFETs with extremely shallow junction and low parasitic resistance have been realized utilizing selective silicon growth(SSG) with rapid thermal anneal(RTA) processing. In the technology, SSG greatly contributes to reduction of effective junction depth for MOSFETs because of raised source/drain(S/D) structures, and RTA can effectively reduce the junction depth, S/D resistance, and contact resistance due to its excellent activation characteristics of implanted ions and anneal-out of fluorine induced defects. By combining SSG with RTA, shallow P+N junction of 0.1µm depth, sheet resistance of 56ohm/square, and contact resistance of 30ohms for 0.8µm2contact were achieved simultaneously. Moreover, this device structure can provide relaxed alignment tolerances as well as more reliable contact characteristics by avoiding aluminum spiking. The feasibility of the fabrication process and device structure has been demonstrated.

Via hole-related simultaneous stress-induced extrusion and void formation in Al interconnects

A reliability issue caused by high temperature annealing after via hole opening is investigated. A high temperature anneal above 450 degrees C causes simultaneous Al extrusion at the via hole interface and void formation in Al interconnects, drastically degrading the reliability of Al lines with vias. Based on in situ observation of extrusion/void formation and two-dimensional elastic deformation analysis, it was found that this phenomenon is due to the movement of Al atoms towards the via hole interface resulting from the thermal expansion and the stress gradient formed in the Al line near the via hole during the anneal sequence. Experimental results and the influence of such an anneal process on the reliability of Al lines are discussed.<<ETX>>

Simultaneous Stress-Induced Al Extrusion and Void Formation Caused by High Temperature Annealing after Via-Hole Opening in Al Interconnects with Via-Holes

A new reliability issue caused by high temperature annealing after via hole opening has been investigated and characterized. For the first time, it was found that a high temperature anneal above 450° C causes simultaneous Al extrusion at the via hole interface and void formation in Al interconnects, drastically degrading the reliability of Al lines with vias. Based on in situ observation of extrusion/void formation and two-dimensional elastic deformation analysis, it was confirmed that this phenomenon is due to the movement of Al atoms towards the via hole interface resulting from the thermal expansion and the stress gradient formed in the Al line near the via hole during the anneal sequence. Specific experimental results and the influence of such an anneal process on the reliability of Al lines will be discussed in detail.