Ming-Hsien Lee

15.4: Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering

Results on indium-oxide-based transparent oxide TFTs, which the active layer is prepared by DC sputtering, are presented. The fabricated TOS TFTs show high mobility (37 cm2/V-s), high ON/OFF current ratio and large on-state current. Fabricating oxide TFTs on temperature-sensitive substrates is also attainable owing to the low temperature process of the active layer preparation.

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler-Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.

Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation

This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under off -state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant on-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I- V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.

Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress

This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Effect of Lateral Body Terminal on Silicon–Oxide–Nitride–Oxide–Silicon Thin-Film Transistors

We investigate lateral-body-terminal silicon-oxide-nitride-oxide-silicon thin-film transistors (LBT SONOS TFTs) under erasing operation. These devices have superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by the electric field in the deep-depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. In addition, the lateral body terminal exerting bias can enhance the erasing efficiency and is confirmed by different erasing conditions and structures. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed.

16.1: Distinguished Paper: Rollable Electrophoretic Display with Amorphous‐Silicon Gate Driver Circuit Integrated

Highly flexible electrophoretic display with gate driver circuits integrated was demonstrated. Beginning from the essential components such as TFTs, resistors and capacitors, the authors finally design a GOA-embedded display which can withstand 10,000 rolling cycles of 20 mm radius without any line defect and optic performance degradation.

22.4: In‐Cell Multiple Ambient Light Sensor (ALSs) LCD Integration Using Si‐based Photonic Sensor by a‐Si TFT Technology

We have developed a new AMLCD with multiple ambient light sensors (ALSs) for reducing backlight (BL) power consumption, and false sensing of ambient illuminance. ALSs perform well in showing BL control for power-saving, even though one of the sensors is covered by a finger shadow. Architecture of integrated ALS with a-Si and LTPS technologies are presented. We fabricate the in-cell, and wide-dynamic-sensing ALSs display using new light sensor technology. Photo-electrical characteristics with well linearity and reliability under long-term operation were observed.

Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect

This article investigates the threshold voltage (V t ) shift induced by a self-heating effect for n-channel low temperature poly-Si thin film transistors (TFTs) and finds that there is a shift of more than 3 V in the negative direction after a self-heating operation of 100 ms. The negative V t shift can be attributed to the charge-trapping effect caused by the holes generated by trap-assisted band-to-band thermionic field emission and trapped in the grain boundary of the poly-Si film substrate. We used lateral body contact structure to verify that this unusual V t shift is related to the holes trapped in the substrate.