Ming-Tsung Wu

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and gm. Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

A novel junction-free BE-SONOS NAND flash

We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.

Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.

Scaling evaluation of BE-SONOS NAND flash beyond 20 nm

We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit and ISPP (incremental step pulse programming) for MLC storage are demonstrated for 20 nm BE-SONOS NAND operation. Read current stability and read disturb life time are also evaluated. The estimated number of storage electrons is only 50-100, and for the first time we have demonstrated successful data retention after 150degC baking in the ldquofew-electronrdquo regime. Our results strongly suggest that BE-SONOS is a promising charge-trapping (CT) technology for NAND Flash scaling.

A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface

For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance degradation mainly comes from Dit generation at Si/O1 interface, while charge trapping in the thin ONO barrier is negligible even after 100K cycles of stressing. Meanwhile, the high-temperature VT loss mainly comes from interface state annealing, while the real charge loss due to electron de-trapping is much smaller. This indicates that our nitride-trapping device has “deep” traps that well retain charges even after the tunnel barrier is damaged. Based on this understanding, we have introduced nitrided O1 to strengthen the Si/O1 interface, and both the endurance and retention are greatly improved. We demonstrate high-endurance BE-SONOS NAND devices of P/E ≫ 5K for MLC and P/E ≫ 100K for SLC operations with excellent retention, promising for solid-state drive (SSD) applications.

A novel planar floating-gate (FG) / charge-trapping (CT) NAND device using BE-SONOS inter-poly dielectric (IPD)

Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits of CT and FG - CT for good retention and scaling to few-electron regime and FG for edge effect immunity and faster erase. The planar “fusion” FG/CT devices are fabricated by replacing the conventional IPD ONO of a FG device by a CT BE-SONOS structure. Both simulation and experimental results indicate that most of the stored electrons are trapped inside the SiN trapping layer instead of the FG. The CT storage provides excellent retention even for a very thin tunnel oxide (≪5nm). On the other hand, the thin FG provides an equipotential channel that screens any non-uniform injection effect. Excellent memory window, scalability and reliability are demonstrated.

A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Sub-40nm body-tied FinFET BE-SONOS NAND Flash is studied extensively. BE-SONOS offers efficient hole tunneling erase and excellent data retention. When integrated into a FinFET structure, the inherent field enhancement (FE) effect around the fin tip provides very faster program/erase speed. However, the non-uniform injection around the fin also greatly complicates the operation of FinFET BE-SONOS. In this work, the switching mechanisms at the fin tip, sidewall and bottom corner are examined in detail, thus providing insights to optimize the FinFET geometry. For the first time, we demonstrate that the ISPP together with self-boosting program-inhibit methods provide excellent Vt distribution control for MLC application for a FinFET CT device.

A Novel Trapping-Nitride-Storage Non-Volatile Memory Cell Using a Gated-Diode Structure With an Ultra-Thin Dielectric Dopant Diffusion Barrier

A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure.

A study of barrier engineered Al 2 O 3 and HfO 2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness

The behavior of barrier engineered charge trapping devices incorporating Al<inf>2</inf>O<inf>3</inf> and HfO<inf>2</inf> high-K layers has been critically examined. We propose to use a thicker buffer oxide (≫ 6 nm) and thin (≪5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO<inf>2</inf> has a better thickness scaling capability than Al<inf>2</inf>O<inf>3</inf>. Finally, a high-performance BE-SHONOS (with n⁺-poly gate and HfO<inf>2</inf> top capping layer) transistor is demonstrated in this work.