Jung-Yu Hsieh

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and gm. Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are achieved, owing to the good control capability of the tri-gate FD structure. Successful NAND array functions are demonstrated, with more than 1 muA read current for a 16-string NAND array and good program disturb immunity. This new device also shows good endurance and data retention, and negligible read disturb. These results are very encouraging for future 3D flash memory

A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET

Theoretical calculation indicates that when the fin width is comparable to the EOT of the ONO, the bottom oxide electric field around the fin tip is significantly increased, resulting in the enhanced program/erase efficiency. We also discover that the non-uniform injection along the fin changes DC characteristics (S.S. and gm) during program/erase, and the effective channel width of FinFET SONOS is only around the fin tip. We integrate BE-SONOS in a body-tied FinFET structure with a very small fin width (<20 nm), and demonstrate a high-speed NAND Flash (<20 musec programming time and <2 msec erasing time for a 5 V memory window). The present work provides not only physical insights into the operation mechanisms of FinFET SONOS-type devices, but also a new design method for high-speed NAND Flash.

A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

The erase and retention characteristics of MONOS, MANOS and BE-SONOS devices are examined in detail in order to determine their mechanisms. The erase transient current (J) is extracted and plotted against the tunnel oxide electric field (ETUN). Our results show that the erase speed ranking is BE-SONOS > MANOS > MONOS. The difference in erase speed comes from the different erase mechanisms of these devices. The retention characteristics are also compared and discussed.

A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand -Type Flash Memory

A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash

Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.

MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation

A bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) using Al2O3 top blocking layer and metal gate (MA BE-SONOS) is proposed to provide very fast erase speed without erase saturation. Compared with MANOS (Shin et al., 2005) using a thick (4.5 nm) tunnel oxide, MA BE-SONOS shows dramatically faster erase speed, owing to the help of bandgap engineered ONO barrier that facilitates hole tunneling. Compared with BE-SONOS using P+-poly gate and top oxide, MA BE-SONOS does not show any erase saturation, owing to the help of metal gate and AI2O3 blocking layer, which greatly reduce gate injection during erase. Very large memory window (>7 V) can be achieved with excellent data retention. MA BE-SONOS overcomes the erase difficulty in SONOS-type devices, and is highly potential in the future flash memory technology.

Physical and electrical characteristics of silicon oxynitride films with various refractive indices

This study explores the relationship between both the physical and the electrical characteristics of silicon oxynitride (SiON) films and the refractive index. The single wafer rapid thermal process modules were used for low pressure chemical vapour deposition of SiON films. A series of SiON films with refractive index between 1.50 and 1.83 were fabricated. Fourier transform infrared absorption spectroscopy and x-ray photoelectron spectroscopy identified the chemical bonding configurations of different SiON films: the Si–N bonds are replaced by Si–O bonds as the refractive index of the SiON films declines. Moreover, the Si atomic ratio is kept between 35% and 40% while the oxygen atomic ratio increases and the nitrogen atomic ratio decreases as the refractive index of the SiON film declines. The electrical characteristics of different SiON-based silicon–oxide–nitride–oxide–silicon (SONOS) devices suggest that (1) the dielectric constant increases with increasing refractive index of the SiON film and (2) the charge-trap density is inversely proportional to the oxygen concentration in the SiON film. Based on these results, the SiON films with various refractive indices can provide a wider application for silicon-based devices, such as SONOS and MOS devices.