Dirk Wristers

Ge MOS characteristics with CVD HfO/sub 2/ gate dielectrics and TaN gate electrode

In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics and TaN gate electrode. Using the newly developed pre-gate cleaning and NH/sub 3/-based Ge surface passivation, the TaN/HfO/sub 2//Ge gate stack with EOT of 12.9 /spl Aring/ exhibits excellent leakage current density of 6 mA/cm/sup 2/ @Vg=1V and interface state density (D/sub it/) of 8/spl times/10/sup 10//cm/sup 2/-eV. Both D/sub it/ and CV hysteresis of Ge MOS are improved significantly with NH/sub 3/ surface treatment. We also study the effects of post-deposition anneal and investigate the conduction mechanism of TaN/HfO/sub 2//Ge gate stack.

Electrical properties and reliability of MOSFET's with rapid thermal NO-nitrided SiO/sub 2/ gate dielectrics

This paper reports on the performance and hot carrier reliability of N- and P-channel MOSFETs with oxynitride gate dielectrics fabricated by rapid thermal nitridation (RTN) of thermally grown SiO/sub 2/ in pure nitric oxide (NO) ambient. It is found that current drivability of N-channel MOSFETs increases with NO-nitridation of SiO/sub 2/. A significant enhancement in high field electron mobility is also observed with increasing NO-nitridation. P-channel MOSFETs with NO-nitrided SiO/sub 2/ gates show somewhat lower current drivability and hole mobility compared to SiO/sub 2/ for both low- and high-V/sub g/. Both N- and P-channel MOSFETs with NO-nitrided oxides show excellent immunity to channel hot carrier degradation. The improvement in hot-carrier reliability is attributed to the efficient incorporation of nitrogen in the dielectric through NO-nitridation. A 1000/spl deg/C, short 10-second NO-anneal was found to be the optimum nitridation condition since, compared to control oxide devices, these devices showed comparable electron and hole mobility but significantly enhanced hot-carrier immunity. >

Boron segregation in As-implanted Si caused by electric field and transient enhanced diffusion

Boron segregation in an implanted arsenic profile in Si during annealing was investigated under various annealing conditions. It was found that both the implant damage created by arsenic implantation and arsenic deactivation enhance the diffusion of the embedded boron layer toward the shallow As implanted profile. The segregation phenomenon was observed in both 650 °C furnace annealed (FA) and 1000 °C rapid thermally annealed (RTA) samples. For the 650 °C FA sample, the boron segregation peak was located at the junction formed by implanted As, where residual dislocation loops at the original amorphous/crystalline (a/c) interface were also observed. However, no a/c interface dislocation loops were found to be present for the RTA samples. Additional anomalous boron segregation was observed for the 1000 °C RTA+750 °C FA samples. The additional boron segregation is not correlated with defect layers. It is, therefore, concluded that the anomalous boron segregation is caused by the electric field resulting from...

Effect of local interconnect etch-stop layer on channel hot-electron degradation

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N2O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

The effect of hydrogen denudation on thin oxides, device performance, and epitaxial elimination

With the cost of each new technology generation increasing at an alarming rate, it has become imperative that technologies that provide for process simplification and material cost reduction be investigated. With the switch from diffused wells to implanted retrograde wells the potential for epitaxial material replacement exists. The impact of pre-process high temperature annealing in a hydrogen ambient has been demonstrated to provide for improved material performance as compared to conventional CZ material. Improvements in gate oxide quality and diode leakage have been observed through application of the H/sub 2/ anneal. Material analysis such as TEM, SIMS impurity profiling, denuded zone analysis, and surface studies suggest that the mechanism for the improved performance of the H/sub 2/ annealed wafer is due to improvements in oxygen denuded zone formation and silicon surface quality.

Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile

The benefits of super steep retrograde channel profiles on MOS transistor performance as reported in the literature have been inconsistent. This inconsistency is in part due to the sensitivity of the performance benefit to the process parameters and integration of the retrograde channel profile. As exhaustive study that integrated and optimized a p-ch arsenic retrograde channel profile transistor into a high performance sub 0.18micrometers transistor CMOS microprocessor process was performed. It was found that the dose and energy of the retrograde channel implant significantly affected the performance improvement obtained. A higher SSRC implant dose, or lower implant energy resulted in higher drive current for a given off current relative to a conventional channel profile control transistor. In addition, the improvement in the transistor linear current was even more significant. At IDOFF equals 1nA, the IDS and IDLIN improvement was approximately 10 percent and 16 percent, respectively. Improvement in transistor drive current also increased at higher drive current. The saturated threshold voltage and Drain Induced Barrier Lowering roll-off with effective channel length were superior for the retrograde channel profile versus the conventional channel profile transistor. Gate oxide reliability with the arsenic doping was also evaluated using Voltage Ramped Dielectric Breakdown (VRDB). It was found that the p-ch gate oxide capacitor VRDB failure rate with the arsenic retrograde channel doping profile was as good or better compared with the conventional phosphorous doped channel profile.

Hydrogen denudation for enhanced thin oxide quality, device performance, and potential epitaxial elimination

We report on the use of hydrogen denudation processing (annealing) that significantly improves CMOS bulk Cz wafer quality. Superior device performance, thin tunnel/gate oxide quality and Cz wafer surface properties have been measured demonstrating the potential for epitaxial elimination. This is achieved by subjecting the wafers to a short hydrogen denudation pre-process between 1050 C and 1200 C for 15 to 30 minutes. For thin oxides down to 8.2 nm up to 29% improvement was observed on two different QBD structures. Hydrogen denuding was also very effective in eliminating mode B oxide breakdown failures on bulk non-epitaxial Cz wafers. Additionally, an order of magnitude decrease in junction leakage was observed for the H/sub 2/ annealed wafers relative to the bulk non-epitaxial Cz wafers, resulting in bulk Cz wafers with surface properties similar to epi wafers without the added cost. SIMS and thermawave analysis coupled with an MeV phosphorus implant were used to characterize the effect of H/sub 2/ anneal on interstitial oxygen at the surface.<<ETX>>

Boron segregation in As-implanted Si due to electric field and transient enhanced diffusion

Boron segregation toward implanted arsenic profile in Si during annealing was investigated under various annealing conditions. It is found that both the implant damage created by the arsenic implantation and arsenic deactivation enhance the diffusion of the embedded boron layer toward the shallow As implanted profile. This phenomena was found in both 650 degree Celsius furnace annealed (FA) and 1000 degree Celsius rapid thermally annealed (RTA) samples. For the 650 degree Celsius FA sample, the boron segregation peak was found located at the junction formed by implanted As, where residual dislocation loops at the original amorphous/crystalline (A/C) interface was also observed. However, no A/C interface dislocation loops were found to be present for the RTA samples. Additional anomalous boron segregation was observed for the 1000 degree Celsius RTA plus 750 degree Celsius FA samples. The additional boron segregation is not correlated with defect layers. It is, therefore, concluded that the anomalous boron segregation is caused by the electric field resulting from the formation of p-n junction.

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

Material processing and advanced well structures using high-energy implantation for EPI replacement

With the cost of each new technology generation increasing at an alarming rate, it has become imperative that technologies which provide for process simplification and material cost reduction be seriously investigated. Many of the next generation technologies for logic as well as memory applications have incorporated some vertical modulation of the well dopant concentration. This type of structure can provide process simplification and an improved isolation strategy, but with more aggressive engineering of the substrate dopant concentration and the current gain of the parasitic bipolar transistors that exist in the CMOS structure superior, latch-up immunity has been demonstrated on both simulated and actual devices. Devices with an aggressive 2 micron P+ to N+ spacing were built with this innovative well structure and have been shown to provide outstanding latch-up performance (4X improvement in measured trigger current) as compared to that of devices built with a standard diffused well process. In addition to providing an analysis of the latch-up performance of the advanced well structure, results of an investigation of the impact of high energy implantation on the gate oxide quality, junction quality and bulk material properties is discussed.