Kwanyeob Chae

A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching

This paper presents a dynamic timing control technique to prevent timing errors in a pipeline under variations. Timing errors in a pipeline are prevented by borrowing time from the following stage and resolving the borrowed time by stretching the next clock cycle. This paper analyzes the operating principles of the proposed technique; presents the design of the required circuit components; and demonstrates its operation through fabrication and measurement of a prototype test-chip designed in an 180 nm CMOS process. The measurement results demonstrate that a system employing the dynamic timing control technique can operate in a wider frequency and voltage range.

A dynamic timing control technique utilizing time borrowing and clock stretching

In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter to stretch the clock period by TBW. This makes the system delay-error tolerant at a lower voltage or a higher frequency without any error management. To validate the proposed technique, we designed a prototype in a 180-nm CMOS technology. At a 10% activation probability of critical paths, the measurement results show a power reduction of up to 22% (at the same clock frequency) or an operating frequency increase of up to 10% (at the same power) compared to those of a conventional design.

All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation

This paper presents an all-digital technique to modulate the system clock and local clocks in response to global and local voltage noise to prevent timing errors during low-voltage operation. The critical path replica circuits are utilized to change the clock period within a clock cycle in response to transient supply noise. Measurement in 130-nm CMOS demonstrates reliable operation of a test pipeline over a wide dc (1.3-0.74 V) voltage range. At 0.81 V, the pipeline operates without timing errors at 7.2% higher frequency even under a 189-mV transient voltage droop.

Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs

In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal-oxide-semiconductor (nMOS) and p-channel metal-oxide-semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs.

Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs

This paper presents tier-adaptive-voltage-scaling (TAVS) as a post-silicon tuning methodology for improving parametric yield of 3D integrated circuits considering die-to-die and within-die process variations. The TAVS methodology senses process corners of individual tiers using on-tier delay sensors and adapt the supply voltage of each tier. The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed. Circuit level simulation and statistical analysis of the TAVS architecture in predictive 45nm technology show the possibility of 26%-39% reduction in chip delay distribution.

Characterization of Inverse Temperature Dependence in logic circuits

As the supply voltage (VDD) approaches the device threshold voltage (VT), the elevated temperature results in increased device current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with a built-in poly-resistor-based heater to characterize ITD in digital circuits. Our measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation. A more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.

Timing error prevention using elastic clocking

“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking. Time borrowing allows a pipeline to compensate the timing slack by borrowing time from the next pipeline stage and clock stretching pays back the borrowed time to the next pipeline stage. Thus, a system employing such dynamic timing control technique can prevent errors with a small performance penalty and eventually operate without safety margin. The net effect is better power-performance trade-off under voltage scaling i.e. lower power consumption for a target frequency or higher operating frequency for a target power. The proposed technique was validated using a prototype test-chip designed in 180-nm CMOS technology.

Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating

A technique is presented to prevent timing errors under transient noise by borrowing time over multiple stages and by compensating once by delaying the clock gating over multiple cycles from the time-borrowing detection point. A logic network is presented for programming the number of stages n, over which time borrowing is performed to trade off supply noise tolerance with a performance penalty. The constraint that is associated with the control delay from the time-borrowing detection to the clockgating circuit is also relaxed to n cycles. The technique is referred to as the programmable time borrowing (PTB) technique, as time borrowing is performed over a programmable number of stages. A test chip with a five-stage pipeline employing the PTB is designed in the 130-nm CMOS technology, and the measurement results demonstrate improved noise tolerance and effective performance.

Analysis of the Performance, Power, and Noise Characteristics of a CMOS Image Sensor With 3-D Integrated Image Compression Unit

This paper investigates the design of logarithmic CMOS image sensor with 3-D integrated image compression unit. The image sensor consists of a pixel array, column circuits, an array of analog-to-digital converters, a frame memory (image buffer) array, and a signal processing unit for image compression. This paper analyzes the correlation between the power dissipation in the image compression unit and the spatial noise characteristics of the photodiode array in the 3-D image sensor. The coupled power, performance, thermal, and noise analysis is performed considering 180-nm CMOS technology. The coupled analysis shows that, due to die-to-die thermal coupling, 3-D stacking of the image compression unit, although provides for better energy efficiency, results in a strong interaction between image quality, desired image throughput, and environmental factors, such as lighting conditions or available channel bandwidth.

An antenna mismatch immuned CMOS power amplifier

A 2.4 GHz reconfigurable CMOS power amplifier to minimize antenna mismatch effects is presented. The PA is implemented by using a 0.18-μm RF CMOS process, and the supply voltage is 3.3 V. The proposed PA is compared to a conventional PA with a fixed matching network. By utilizing the proposed reconfigurable matching network, both the efficiency and the output power are improved under an antenna mismatch condition while satisfying the linearity specifications. For example, the maximum linear power and PAE are increased from 11.1-dBm to 16.1-dBm and from 8.1% to 19% at a Γ=0.3ζ45 condition, respectively. To our knowledge, this is the first fully-integrated CMOS PA with a reconfigurable matching network that improves the robustness to the antenna mismatch.