Shih-Hung Chen

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the worlds first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BLs (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasonable number of stacked memory layers (≤ 32) and thus potentially offers lower cost. VG NAND has good pitch scalability thus is very attractive. On the other hand, it is more difficult to decode the bit line in a VG architecture, thus decoding innovations are required for a compact array architecture design. This paper provides a systematic comparison of four different decoding methods of VG NAND. Performance of the TFT BE-SONOS device used in 3D VG NAND is also addressed.

Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform CBLs for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

A new thin-film, cross-point non-volatile memory using threshold switching properties of phase-change chalcogenide

A new cross-point, nonvolatile, phase-change memory is investigated. This new memory exploits the properties of the newly discovered controllable threshold voltage for chalcogenide material (Chen et al., 2003). Using this unique property, the device is itself both an access element and a memory element and no access transistor is needed in the memory cell. Very fast programming and reading speed are demonstrated. This simple memory is also non-volatile, random accessible, and highly scalable. The cell size is only 4F/sup 2/.