Masataka Kase

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

A novel CMOS architecture utilizing tensile/compressive silicon nitride capping layers to induce tensile/compressive strain in NMOSFET/PMOSFET channel regions was developed. NMOSFET device delivers 1.05mA//spl mu/m on-current for 70nA//spl mu/m off-current at IV drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N- and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub-40nm gate length.

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

Eliminating channeling tail by lower dose preimplantation

We optimized Ge+ and Si+ preimplantation to eliminate the channeling tail and prevent the rapid diffusion of boron and the formation of serious defects. We examined the dependence of the microchanneling of BF+2 implantation or the lattice disorder of preimplanted silicon using secondary‐ion mass spectroscopy and grazing exit Rutherford backscattering spectroscopy. The optimum doses are about 25% those for full amorphization, i.e., preamorphization. The channeling tail is eliminated by disordered layers containing about 60% silicon atoms on irregular sites.

Ultra-low contact resistance for deca-nm MOSFETs by laser annealing

We demonstrate an ultra-low contact resistance of 4/spl times/10/sup -8/ /spl Omega/-cm/sup 2/ (5/spl times/ lower than RTA) using a laser annealing (LA) process. The contact resistance reduction is attributed to the high activated dopant concentration of 10/sup 21/ cm/sup -3/. For the first time, we have successfully fabricated LA-pMOSFETs with a conventional CMOS integration flow for lowering contact resistance.

Photoresist Removal Using Atomic Hydrogen Generated by Hot-Wire Catalyzer and Effects on Si-Wafer Surface

We investigated an environmentally friendly method using atomic hydrogen generated by contact catalysis on a tungsten hot-wire catalyzer to remove photoresist instead of using chemicals and its effects on a Si-wafer surface. We eventually obtained a photoresist removal rate of 2.5 µm/min attributable to a reaction of atomic hydrogen with a positive-tone novolak photoresist, without thermal shrinkage of the photoresist film during atomic hydrogen irradiation because the photoresist shrank only under the influence of substrate heating by the catalyzer. The effects of atomic hydrogen irradiation on the substrate surfaces cannot be confirmed.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

This paper presents a 65 nm CMOS technology for mobile multimedia applications. The reduction of interconnect capacitance is essential for high-speed data transmission and small power consumption for mobile core chips. We have chosen a hybrid ULK structure which consists of NCS (nano-clustering silica; k=2.25) at the wire level and SiOC (k=2.9) at the via level. Although NCS is a porous material, the NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bonding. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistors meet the electrical targets from the circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 /spl mu/m/sup 2/ small cell size has been achieved.

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with 25/33 nm gate nMOSFETs were achieved at Vdd=1 V and Ioff=100 nA//spl mu/m. They are the best values among recent published papers.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

A study of ultra shallow junction and tilted channel implantation for high performance 0.1 /spl mu/m pMOSFETs

The impact of ultra-shallow junction and tilted channel implantation (TCI) is discussed with respect to source/drain resistance (R/sub sd/), and short-channel effect (SCE) based on physical gate length (L/sub gate/) and effective gate length (L/sub eff/). We obtained the following results: (1) A shallower junction improves the SCE immunity for a given L/sub gate/, but not with respect to L/sub eff/. (2) The essential factor for the reduction of R/sub sd/ is not the sheet resistance (R/sub sheet/) of source/drain (S/D) extensions, but the junction tailing profile. (3) TCI was found to be effective for increasing the current drive ability due to the reduced L/sub eff/ for a given off current (I/sub off/). (4) The effectiveness of TCI was confirmed by a CV L/sub eff/ extraction method. (5) Encouraged by the above results, high-performance 0.1 /spl mu/m pMOSFETs were demonstrated using a 1 keV, B/sup +/ or BF/sub 2//sup +/ implantation and TCI technology. The device achieved a high drive current (I/sub drive/) of 360 /spl mu/A//spl mu/m (@V/sub g/=V/sub d/=1.5 V, I/sub off/=1nA//spl mu/m).