Kazuo Terada

A New Method to Determine Effective MOSFET Channel Length

An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

Comparison of MOSFET-threshold-voltage extraction methods

Abstract The difference in MOSFET threshold voltages caused by the difference in the extraction method is studied, by measuring and analyzing its dependencies on channel length, substrate voltage and drain voltage. It is found that the standard deviation of the difference between threshold voltages caused by the difference in the extraction method is less than that of the threshold voltage itself in a wafer. The dependencies of the threshold voltage on channel length, extracted from the drain current data around the threshold voltage, however, show different behavior from those extracted from the drain current data only in the subthreshold region or only in the ON region. It is considered that “channel-length modulation” causes this different behavior and, therefore, that those extraction methods are not desirable.

Analyses of 5σ V th fluctuation in 65nm-MOSFETs using takeuchi plot

Using 1M DMA-TEG, the analyses of 5sigma Vth fluctuation in 65 nm-MOSFETs were carried out. Physical and electrical analyses confirmed that random dopant fluctuation is dominant though NMOSFET has larger fluctuation as compared with PMOSFET. To explain this phenomenon, a B clustering model is proposed. In the case of clustering with 5 to 6 B atoms in the channel, Vth fluctuation of NMOSFET can be explained.

Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method

Causes of drain current local variability are analyzed by decomposing into current variability components. Besides VTH and Gm components, it is newly found that effects of “current onset” variability caused by channel potential fluctuations largely contribute to the current variability and that Gm component is relatively small in the saturation region. It is shown that both VTH and current onset components decreases with reducing channel dopants, indicating that intrinsic channel is very effective to reduce current variability.

A test circuit for measuring MOSFET threshold voltage mismatch

A new test circuit is proposed for evaluating MOSFET threshold voltage mismatch. This test circuit consists of many parallel-connected unit cells, in which two MOSFETs are serially-connected with each other and the node between them is connected to common wiring through a switch. The threshold voltage mismatch for the two MOSFETs is derived from the DC currents flowing through this test circuit. Experimental results confirm the merit of this test circuit.

Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

The origin of larger on-state drain current (ION) variability in n-type field-effect transistors (NFETs) than that in p-type field-effect transistors (PFETs), is investigated by evaluating FETs fabricated using 65 nm technology. It is found that the larger ION variability in NFETs is caused by not only the larger threshold voltage component but also the larger current-onset voltage component of the ION variability in NFETs. Moreover, it is experimentally confirmed that ION variability of NFETs can be reduced by the halo carbon co-implantation through the reduction of threshold voltage and current-onset voltage components of the ION variability in NFETs.

Evaluation of MOSFET C-V curve variation using test structure for charge-based capacitance measurement

Test structure for charge-based capacitance measurement (CBCM) is improved, to achieve higher accuracy of measuring capacitance-voltage (C-V) curves for actual size MOSFETs. Capacitance mismatch between the device under test (DUT) and the reference is avoided by using charge-injection-induced-error-free CBCM (CIEF CBCM) method. To increase the applicable bias voltage range to DUT, both P- and N-channel MOSFETs are parallel-connected in the pseudo-inverter. It is found that the C-V curves, which are measured with this test structure and are corrected by removing the size effect, are very close to the C-V relation measured by the conventional method, and then, the corrected capacitances give more accurate gate capacitances of MOSFETs.

High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

The properties of drain current variability in field-effect transistors (FETs) at high temperature are experimentally investigated. It is found that the on-state drain current (ION) at high temperature has a strong correlation with ION at room temperature and that there is no anomalous ION change from room temperature to high temperature. It is also found that ION variability at high temperature is smaller than that at room temperature. The origin of the decrease in ION variability with increasing temperature is analyzed by the decomposition method developed in our previous work. It is clarified that the decrease in the current–onset voltage component plays a dominant role, especially in the saturation region. Moreover, it is also clarified that thermal excitation of carriers suppresses current–onset voltage variability, and ultimately the current–onset voltage component of ION variability with increasing temperature.

A test circuit for measuring standard deviations of MOSFET channel conductance and threshold voltage

A new test circuit is proposed for measuring the standard deviations of both MOSFET channel conductance and threshold voltage. This test circuit consists of the matrix-shape MOSFET array in which several switches and wiring are added. DC currents flowing through this array are measured, changing the ON/OFF states of the switches, and then the standard deviations are calculated from them.

Origin of “current-onset voltage” variability in scaled MOSFETs

Present work analyzes the cause of “current-onset voltage” variability, which has been newly found to largely affect drain current variability [1]. It is found by 3D device simulation that the “current-onset voltage” variability is determined by how largely the channel potential fluctuates by random dopant disposition. Reducing RDF will suppress both threshold voltage and current-onset voltage variability as well.