Nobuo Tamba

High speed BiCMOS VLSI technology with buried twin well structure

Bipolar transistors of high cut off frequency (f_{T}=9GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.

A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS

A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum standby current is introduced. Previously-reported application of this technique is to limited to static circuits. Here it is applied not only to static circuits, but also to clock-distribution drivers, register files and dynamic circuits in RAM macros. Precise clock-skew control, PLL jitter minimization, and optimized buffer insertion on long wires are carried out in accordance with the critical path analysis.

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5- mu m BiCMOS technology achieved a 1.5-ns access time with a 78- mu m/sup 2/ memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers. >

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers. >

A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

The authors present a chip with 1.5-ns access SRAM (static random access memory) and 60-ps logic gates that uses a BiCMOS memory technology with ECL (emitter coupled logic)-CMOS circuits and a 0.5- mu m BiCMOS process providing double-polysilicon bipolar transistors. The chip consists of a gate array and two RAM blocks. The RAM block has four RAM macros, a custom logic macro and a write-pulse generator. A RAM macro contains two 1-kW*32-b arrays with bit redundancy and peripheral circuits. Input/output circuits are at the chip periphery. The RAM operates over a wide range of the supply voltage. Measured output-latch path delay is 2.4 ns at VEE=-4 V. RAM access time is 1.5 ns. Write pulse width is 1.3 ns.<<ETX>>

A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

A 0.35 /spl mu/m ECL-CMOS technology has been developed to achieve high speed and high density LSIs for mainframe computers. A high speed bipolar transistor with cutoff frequency f/sub T/ of 30 GHz and a 30 /spl mu/m/sup 2/ 6T-CMOS memory cell with a trench isolation are introduced onto an SOI substrate. This technology has been applied to a 40 ps, 120 K gate logic LSI and a 1 ns, 2.3 Mbit SRAM with 50 K gate array.

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-/spl mu/m BiCMOS process. The memory cell size is 58 /spl mu/m/sup 2/ and the chip size is 11/spl times/11 mm. >

A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

With continuous scaling of process technology, embedded DRAM technology becomes promising for high performance cache memory systems because of its potential of large memory capacity and high bandwidth. Although several papers reported, none of them has enough memory bandwidth or capacity for high-end computer applications. This 16 MB cache DRAM LSI chip with internal 35.8 GB/s memory bandwidth and 9.0 ns DRAM random access latency uses merged logic DRAM process technology that combines leading-edge DRAM devices equivalent to that of 256 Mb conventional DRAM with high-speed 0.2 /spl mu/m CMOS logic.