Mitsuhiro Nakao
Toshiba
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Publication
Featured researches published by Mitsuhiro Nakao.
electronic components and technology conference | 2008
Yoshiaki Sugizaki; Mitsuhiro Nakao; Kazuhito Higuchi; Takeshi Miyagi; Susumu Obata; Michinobu Inoue; Mitsuyoshi Endo; Yoshiaki Shimooka; Akihiro Kojima; Ikuo Mori; Hideki Shibata
Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.
Archive | 2005
Mitsuhiro Nakao
Archive | 1995
Mitsuhiro Nakao; Toshimitsu Ishikawa; Kazunori Hayashi
Archive | 2002
Hiroshi Toyoda; Mitsuhiro Nakao; Masahiko Hasunuma; Hisashi Kaneko; Atsuko Sakata; Toshiaki Komukai
Archive | 2009
Mitsuhiro Nakao; Junya Sagara; Katsuhiro Ishida; Noboru Okane
Archive | 2007
Yukako Tsutsumi; Mitsuyoshi Endo; Mitsuhiro Nakao
Archive | 2006
Mitsuyoshi Endo; Mitsuhiro Nakao; Yukako Tsutsumi; 由佳子 堤
Archive | 1998
Mitsuhiro Nakao; Toshimitsu Ishikawa; Kazunori Hayashi
Archive | 2012
Norihiro Togasaki; Mitsuhiro Nakao; Yosuke Morita
Archive | 2008
Hiroshi Toyoda; Mitsuhiro Nakao; Masahiko Hasunuma; Hisashi Kaneko; Atsuko Sakata; Toshiaki Komukai
