Mitsuhiro Noguchi

A 120mm 2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

A 19 nm 112.8 mm

NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.

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Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.

64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide.

A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

We have investigated the far-infrared (FIR) photoresponse of the magnetoresistance of the quasi-one-dimensional electron systems in AlGaAs/GaAs split-gate single quantum wire (QWR) structures. It was found that the QWR structures exhibit photoinduced resistance change due to resonant FIR absorption between the magnetoelectric subbands. From a spectroscopic analysis based on the generalized Kohns theorem, the lateral bare confinement potential, V b, in the split-gate QWR structures has been determined directly. The V b obtained is in good agreement with a theoretical prediction based on simple electrostatics, indicating that FIR spectroscopy is a suitable tool for characterizing the electronic structures in quantum wire structures.

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

We proposed and successfully demonstrated a method to collimate electron waves propagating in a two-dimensional (2D) electron waveguide, using equivalent Snells law for equilibrium electrons. The angular distribution of ballistic electrons emitted into a 2D electron gas formed at a high-quality AlGaAs/GaAs heterointerface was measured under a magnetic field, and an electron collimation effect was experimentally confirmed. The electron collimation can be controlled by changing the voltage applied to a collimation gate which is placed in front of the electron injector. This technique can be applied to a double-quantum-well electron-wave switch for improving the switching ratio.

Direct Determination of Bare Confinement Potentials in AlGaAs/GaAs Split-Gate Quantum Wires by Far-Infrared Spectroscopy

An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm2 /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1.5 μm2cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough ±100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF at 128 wordlines per bitline. An undershoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme to obtain a half of “1” data (not an average of “1” and “0” data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test vehicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2 × 10-18 bit error rater (BER) by soft error and 10 ms data retention at 85 °C are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access.

Collimation of Two-Dimensional Ballistic Electrons Using Equivalent Snell's Law

A hybrid Schottky barrier tunneling transistor is assessed by device simulations and measurements. n+ regions are formed in Schottky contact regions of source and drain. The unified simulation technique is used to simulate ohmic and Schottky contact natures. The devices are fabricated by utilizing the conventional extension process. It is shown that potential modulation by n+ regions reduces drain leakage current and enhance the tunneling probability at the source contract.