Myungsim Jun

Electrical and structural properties of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

The authors investigate the electrical and structural properties of high-k Er-silicate film formed by the interfacial reaction between Er and SiO2 films. The increase in rapid thermal annealing temperature leads to the reduction of the interface trap density by one order of magnitude, indicating the improvement in the interface quality of Er-silicate gate dielectric. The increased capacitance value of Er-silicate gate dielectric with thermal treatment is attributed in part to the reduction of SiO2 thickness and to the increase in the relative dielectric constant of Er-silicate film caused by the chemical bonding change from Si-rich to Er-rich silicate.

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.

Analysis of temperature-dependent barrier heights in erbium-silicided Schottky diodes

We manufactured erbium-silicided Schottky diodes on n-type and p-type silicon substrates to determine the Schottky barrier heights for electrons and holes, respectively. The effective barrier heights were extracted from the current-voltage-temperature characteristics of the Schottky diodes in reverse-bias condition. The barrier heights were obtained as a function of temperature, decreasing with the decrease of temperature. Low effective barrier heights at low temperature may be due to the trap-assisted current at the erbium silicide/silicon Schottky junction. The temperature-independent barrier heights for electrons and holes were evaluated to be 0.39 and 0.69eV, respectively, at high temperature by fitting the effective barrier heights as a function of temperature. In this case, the carrier conduction mechanism can be explained by the pure thermionic emission model.

Characterization of electrical and structural properties of strained-Si-on-insulator layers

The electrical and structural properties of strained-Si-on-insulator (sSOI) wafers were investigated. The strain, calculated from two-dimensional reciprocal space mapping, was found to be 0.78%, which is comparable to that of fully relaxed Si1−xGex film with Ge concentration of 20.6at.%. Based on the Raman peak shift combined with measured value of strain, the strain shift coefficient is extracted to be −736cm−1. The pseudo-metal-oxide-semiconductor field-effect transistor measurements, employed to characterize the electrical properties of sSOI wafers, showed that both electron and hole mobilities are enhanced by strain. The enhancement factor of electron mobility is larger than that of hole mobility.

Analysis of interface trap states at Schottky diode by using equivalent circuit modeling

The authors have developed a new equivalent circuit model to analyze the charging dynamics of the interface states in Schottky barrier diodes at reverse bias condition. Trap density and the capture/emission times are extracted by incorporating the measured ac admittance of erbium silicide Schottky diode with the newly developed equivalent circuit model. The extracted trap density is 1.5×1012cm−2eV−1 and the capture and emission transition times are 19 and 5.9μs, respectively. Trap density decreases to 6.1×109cm−2eV−1 after N2 annealing.

Effective Metal Work Function of High-Pressure Hydrogen Postannealed Pt–Er Alloy Metal Gate on HfO2 Film

We have investigated the effect of high-pressure hydrogen postannealing (HPHA) on the effective metal work function (Φm,eff) of a Pt–Er alloy metal gate on a HfO2 film. By considering the presence of an interfacial layer (IL) between the HfO2 film and a Si substrate and a negative charge at the HfO2/IL interface, the Φm,eff values of the Pt–Er alloy metal gate before and after HPHA, extracted from the relations of equivalent oxide thickness versus flat-band voltage, are determined to be ~5.1 and ~4.8 eV, respectively. The increase in the density of interface dipole caused by the reduction of PtOx during HPHA could be responsible for the decrease in Φm,eff.

High performance platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect transistors scaled down to 30 nm

Platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect-transistors with sizes varying from 350 to 30 nm were fabricated on silicon-on-insulator substrates. Threshold voltage, subthreshold swing, drain-induced barrier lowering, and saturation current were investigated as a function of gate length and channel width. The device with a gate length of 30 nm showed excellent short channel characteristics with an on/off current ratio larger than 107, an off-leakage current less than 10 pA/μm, and a subthreshold swing of 110 mV/decades.

Effective mobility characteristics of platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect transistor

A 20 μm long channel platinum-silicided p-type Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) is manufactured. The manufactured p-type SB-MOSFET shows 60 mV/decade subthreshold swing characteristic with leakage current less than 10−7 μA/μm and on/off current ratio larger than 106. Using this platinum-silicided p-type SB-MOSFET, the effective mobility of hole is extracted for the first time. The extracted effective hole mobility has slightly lower value compared to universal hole mobility. The reason for this is due to the existence of Schottky barrier between platinum-silicided and silicon.

Pre-silicidation annealing effect on platinum-silicided Schottky barrier MOSFETs

We fabricated platinum-silicided p-type Schottky barrier MOSFETs (SB-MOSFETs) with 40 nm gate length on a silicon-on-insulator wafer. In order to improve the device performance, the devices were annealed at a temperature of 900 °C in a nitrogen environment prior to the platinum deposition for source/drain silicide formation. As a result, lowered threshold voltage of 1.2 V, subthreshold swing values of 110 mV and an enhanced on/off current ratio larger than 107 were obtained. This improvement is attributed to the reduction of the fixed oxide charge in the gate oxide during the annealing process.

Schottky barrier single electron and single hole transistors

Schottky barrier single electron/hole transistor (SB-SET/SB-SHT) are manufactured using erbium-silicide and platinum-silicide as source and drain materials. In room temperature, the manufactured SB-SET and SB-SHT showed typical FET behavior with high drive current, 550 and −376 µA/µm, respectively. At 7 K, these devices showed SET and SHT characteristics. The measured coulomb gaps are about 170 mV for the SB-SET and 220 mV for the SB-SHT. From these, the estimated sizes of the islands are 12.5 and 9.1 nm, respectively. In SB-SET and SB-SHT, high transconductance can be easily achieved because silicided electrode eliminates parasitic resistance. Moreover SB-SET and SB-SHT can be operated as conventional FET and SET/SHT depending on the bias conditions, which is very promising for SET/FET and SHT/FET hybrid applications.