Mouna Kotti

Comparison between PSO and ACO techniques for analog circuit performance optimization

This paper presents a comparison between swarm intelligence (SI) techniques; namely Particle Swarm Optimization and Ant Colony Optimization, to solve analog circuit sizing problems. Performances in terms of optimum quality and computing time of both algorithms are checked via two applications that consist of optimizing performances of a CMOS second generation current conveyor (CCII), and an operational amplifier (Op-Amp).

Physical vs. surrogate models of passive RF devices

The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.

Optimizing CMOS LNA circuits through multi-objective meta heuristics

Particle swarm optimization (PSO) has shown to be an efficient, robust and simple optimization algorithm. Recently, the mono-objective version of the PSO algorithm was adapted and used to optimize only one performance of RF circuits, mainly the voltage gain of low noise amplifiers. In this work, we propose to optimize more than one performance function of LNAs while satisfying imposed and inherent constraints. We deal with generating the Pareto front linking two conflicting performances of a LNA, namely the voltage gain and the noise figure. The adopted idea consists of using the symbolic expressions of the scattering parameters ((S21) for the voltage gain, and (S11, S22) for input and output matching). For this purpose we use a Multi-Objective Optimization algorithm PSO incorporating the mechanism of the crowding distance technique (MOPSO-CD). Comparisons with results obtained using NSGA II are presented and ADS simulations, using 0.35µm CMOS technology, are given to show good reached results.

On the dynamic rounding-off in analogue and RF optimal circuit sizing

Frequently used approaches to solve discrete multivariable optimisation problems consist of computing solutions using a continuous optimisation technique. Then, using heuristics, the variables are rounded-off to their nearest available discrete values to obtain a discrete solution. Indeed, in many engineering problems, and particularly in analogue circuit design, component values, such as the geometric dimensions of the transistors, the number of fingers in an integrated capacitor or the number of turns in an integrated inductor, cannot be chosen arbitrarily since they have to obey to some technology sizing constraints. However, rounding-off the variables values a posteriori and can lead to infeasible solutions (solutions that are located too close to the feasible solution frontier) or degradation of the obtained results (expulsion from the neighbourhood of a ‘sharp’ optimum) depending on how the added perturbation affects the solution. Discrete optimisation techniques, such as the dynamic rounding-off technique (DRO) are, therefore, needed to overcome the previously mentioned situation. In this paper, we deal with an improvement of the DRO technique. We propose a particle swarm optimisation (PSO)-based DRO technique, and we show, via some analog and RF-examples, the necessity to implement such a routine into continuous optimisation algorithms.

Simulation-based multi-objective optimization of current conveyors: Performance evaluations

Multi-objective metaheuristics are over and over again used by analog designers. Pareto fronts linking conflicting parameters are usually generated using different optimisation techniques. Conclusions on these fronts are generally made in a subjective manner; no performance measures are used! In this paper we deal with the use of two metrics, namely the C-metric and the hypervolume indicator. The simulation-based technique is used to generate the non-dominated set of points of the Pareto fronts. Two current mode circuits are considered: a conventional and a differential CMOS current conveyor. The used metrics are detailed, their utility is highlighted, and the results are discussed.

Optimizing CMOS current conveyors through meta heuristics

In this paper, three Meta heuristics are investigated to optimize analog circuit; namely Genetic Algorithms, Particle Swarm Optimization and Simulated Annealing. A particular interest is given to the optimization of performances of current conveyors. SPICE Simulation results are given to show viability of the reached optimal results.

A novel multi-objective algorithm: application to the optimal sizing of current conveyors

This brief proposes a novel multi-objective heuristic. It is a transformation of a mono-objective heuristic into a multi-objective one by addition of an archive and some non dominance computing routines. Performances of the proposed heuristic are demonstrated thru test functions. An application to the optimal sizing of a class AB second generation CMOS current conveyor is presented. Comparison with NSGA-II is given.