Mounir Bohsali

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS

A customized 90nm device layout yields an extrapolated fmax of 300GHz. The device is incorporated into a low-power 60GHz amplifier consuming 10.5mW, providing 12dB of gain, and an output P1dB of 4dBm. An experimental 3-stage 104GHz amplifier has a measured peak gain of 9.3dB. Finally, a Colpitts oscillator at 104GHz delivers up to -5dBm of output power while consuming 6mW.

30 GHz CMOS Low Noise Amplifier

30 GHz low noise amplifier was designed and fabricated in a 90 nm digital CMOS process. The mm-wave amplifier has a peak gain of 20 dB at 28.5 GHz and a 3 dB bandwidth of 2.6 GHz with the input and output matching better than 12 dB and 17 dB over the entire band respectively. The NF is 2.9 dB at 28 GHz and less than 4.2 dB across the band and it can deliver 2 dBm of power to a matched load at its 1 dB compression point. The amplifier has a measured linearity of IIIP3=-7.5 dBm. It consumes 16.25 mW of power using a low supply voltage of 1 V and occupies an area (excluding the pads) of 1600 mum x 420 mum.

Current combining 60GHz CMOS power amplifiers

Two 60GHz power amplifiers are presented in standard 90nm CMOS using integrated power combining and matching networks. The power amplifiers incorporate 4-way/2-way power splitters and combiners into their matching networks rather than using separate structures, and achieve 1dB output power of 12.1/10.1 dBm and saturation output power of 14.2/11.6 dBm respectively with saturation efficiency of 18.1/17.7% respectively when operated with a 1V supply.

A 60 GHz Power Amplifier in 90nm CMOS Technology

A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.

A 60-GHz 90-nm CMOS cascode amplifier with interstage matching

The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption

Nanoscale CMOS for mm-Wave Applications

Aggressive technology scaling of CMOS has culminated in a low-cost high volume commercial process technology with Ft > 150 GHz and Fmax > 200 GHz. This paper discusses the key trends in CMOS scaling that have led to this level of performance and attempts to predict the performance down to 45 nm. The design of active and passive components in CMOS for power gain and low noise are discussed in detail and unique features of CMOS technology are highlighted. Experimental results derived from a 60 GHz amplifier in 90 nm CMOS and a complete 60 GHz front-end receiver in 130 nm CMOS are reported.

Internal Unilaterization Technique for CMOS mm-Wave Amplifiers

An internal unilaterization technique for cas-code devices is analyzed and demonstrated in 90 nm CMOS technology. The substrate network of the device has been incorporated in a circuit technique together with an LC tank on the top gate of the cascode structure. The structure is accurately modeled and conditions for unilaterization of the cascode are derived in terms of the the LC tank parameters. An increase in the maximum stable gain from 7.5 dB to 20 dB has been verified in the measurements using this technique.

Microwave performance of monolithic silicon passive transformers

This paper presents a comparative study between three transformer layout styles, namely the Frlan style, the planar shunt style and the three-dimensional series style, in terms of their minimum insertion loss, gain bandwidth, and transformation ratio over a broad frequency range. A new performance metric, the frequency dependant 1 dB insertion loss bandwidth is presented. Measured insertion loss as low as 2 dB at 20 GHz has been observed. Furthermore, it is shown that with proper layout, a transformation ratio as high as 40:1 is possible over a bandwidth of 40 %.

A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector

A 10Gb/s NRZ receiver with feedforward equalizer and CDR is described. The CDR incorporates an LC oscillator with a range of 8.3 to 11.1 GHz and a new glitch-free binary PFD. The glitch-free architecture minimizes the jitter generation of the CDR and increases jitter tolerance. The CDR loop employs a V/I converter with two independent charge-pumps for FD and PD signals to achieve fast acquisition and low jitter generation simultaneously.