Ehsan Adabi

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS

A customized 90nm device layout yields an extrapolated fmax of 300GHz. The device is incorporated into a low-power 60GHz amplifier consuming 10.5mW, providing 12dB of gain, and an output P1dB of 4dBm. An experimental 3-stage 104GHz amplifier has a measured peak gain of 9.3dB. Finally, a Colpitts oscillator at 104GHz delivers up to -5dBm of output power while consuming 6mW.

Parallel Array InAs Nanowire Transistors for Mechanically Bendable, Ultrahigh Frequency Electronics

The radio frequency response of InAs nanowire array transistors on mechanically flexible substrates is characterized. For the first time, GHz device operation of nanowire arrays is demonstrated, despite the relatively long channel lengths of ∼1.5 μm used in this work. Specifically, the transistors exhibit an impressive maximum frequency of oscillation, f(max) ∼ 1.8 GHz, and a cutoff frequency, f(t) ∼ 1 GHz. The high-frequency response of the devices is due to the high saturation velocity of electrons in high-mobility InAs nanowires. The work presents a new platform for flexible, ultrahigh frequency devices with potential applications in high-performance digital and analog circuitry.

30 GHz CMOS Low Noise Amplifier

30 GHz low noise amplifier was designed and fabricated in a 90 nm digital CMOS process. The mm-wave amplifier has a peak gain of 20 dB at 28.5 GHz and a 3 dB bandwidth of 2.6 GHz with the input and output matching better than 12 dB and 17 dB over the entire band respectively. The NF is 2.9 dB at 28 GHz and less than 4.2 dB across the band and it can deliver 2 dBm of power to a matched load at its 1 dB compression point. The amplifier has a measured linearity of IIIP3=-7.5 dBm. It consumes 16.25 mW of power using a low supply voltage of 1 V and occupies an area (excluding the pads) of 1600 mum x 420 mum.

Broadband variable passive delay elements based on an inductance multiplication technique

A new technique for making broadband and variable passive delay elements is described. By introducing a variable inductance structure and using it along with available varactors, synthesized transmission lines are implemented with variable delay while maintaining a constant Zo over the line bandwidth. Inductance tuning is realized through the effect of mutual inductance. As a demonstration prototype, a single unit cell and two cascaded unit cells were implemented in 90 nm digital CMOS process. Delay values ranging from 14 ps - 40 ps were obtained from DC to 8 GHz while maintaining matched condition over the bandwidth with delay variations of less than plusmn%5. These delay cells could be used in broadband impulse-based beamforming systems to provide variable delays in each RF path.

A 60 GHz Power Amplifier in 90nm CMOS Technology

A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.

A 60-GHz 90-nm CMOS cascode amplifier with interstage matching

The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption

Nanoscale CMOS for mm-Wave Applications

Aggressive technology scaling of CMOS has culminated in a low-cost high volume commercial process technology with Ft > 150 GHz and Fmax > 200 GHz. This paper discusses the key trends in CMOS scaling that have led to this level of performance and attempts to predict the performance down to 45 nm. The design of active and passive components in CMOS for power gain and low noise are discussed in detail and unique features of CMOS technology are highlighted. Experimental results derived from a 60 GHz amplifier in 90 nm CMOS and a complete 60 GHz front-end receiver in 130 nm CMOS are reported.

A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna

There is considerable interest in wideband pulse modulation at mm-Wave frequencies for application in radar and medical imaging systems [1,2]. Accuracy and resolution in these respective systems are determined by the minimum pulse width (PW). PWs down to 300ps have previously been reported for 24/79GHz carrier frequencies [1,3]. This paper presents the design of the first pulse-based transmitter with integrated antenna to achieve sub-100ps PWs at mm-Wave frequencies in silicon. The transmitter generates variable measured PWs in the range of 35 to 376ps. To obtain this performance, hybrid PA/antenna switching has been explored in combination with high-speed digital switching circuitry.

Internal Unilaterization Technique for CMOS mm-Wave Amplifiers

An internal unilaterization technique for cas-code devices is analyzed and demonstrated in 90 nm CMOS technology. The substrate network of the device has been incorporated in a circuit technique together with an LC tank on the top gate of the cascode structure. The structure is accurately modeled and conditions for unilaterization of the cascode are derived in terms of the the LC tank parameters. An increase in the maximum stable gain from 7.5 dB to 20 dB has been verified in the measurements using this technique.