Bagher Afshar

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A Robust 24mW 60GHz Receiver in 90nm Standard CMOS

In this paper, a highly integrated receiver front-end is demonstrated that is manufactured in a digital CMOS process using a design approach amenable to mass production. Unlike many previous attempts in CMOS, the results of the design are well predicted by the simulation results, matching the desired frequency band and the simulated gain to a very high accuracy. Low noise and high gain are demonstrated with low power consumption. The chip is fabricated in a 90 nm digital CMOS process and tested using on-chip probes.

A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging

This paper reports a fully integrated 90 GHz-carrier pulsed transmitter in 0.13 μm SiGe BiCMOS process for imaging applications. To obtain ultra-short programmable pulses, the transmitter employs a number of novel techniques including hybrid switching and Antentronics. The transmit path includes a quadrature VCO, PA driver, PA and the on-chip folded slot antenna. High speed ECL circuits generate and provide the short pulses in several operating modes. The transmitter achieves a record pulsewidth of 26 ps in the hybrid mode and 33 ps in the independent mode. This translates to >30 GHz of RF BW in the transmitter.

X/Ku Band CMOS LNA Design Techniques

This paper reports two 11 GHz low-noise amplifiers (LNA) in 0.18mum CMOS technology. A cascade two stage LNA achieves 12 dB of power gain, 3.5 dB of noise figure, and an input/output match of -15 dB/-27 dB at 11GHz, while consuming 28mA from 1.8V supply. The second LNA is a modified cascode amplifier and it achieves 8 dB of gain, 3.1 dB of noise figure, and an input/output match of -12 dB/-15 dB at 11GHz, consuming 18mA from the 1.8V supply. The paper also discusses design considerations such the effects of layout on frequency tuning and noise

A 2.5mW inductorless wideband VGA with dual feedback DC-offset correction in 90nm CMOS technology

A low power inductorless wideband variable gain control amplifier (VGA) for baseband receivers has been designed in a standard digital 90 nm CMOS technology. The VGA was implemented using four-stage modified Cherry-Hooper amplifier with a dual feedback DC-offset canceling network, which simultaneously corrects DC offsets and extends bandwidth without a peaking inductor resulting in saving the chip space significantly. The proposed VGA has been measured using on-chip probing and achieves a 3-dB bandwidth of more than 2.2 GHz with 60 dB gain tuning range. It consumes 2.5 mW through a 1V supply (excluding the output buffer), and occupies only 0.01 mm2 active area.

Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems

This paper presents the design and analysis of a wideband inductorless variable-gain amplifier (VGA) for high-speed communication receiver systems. The proposed methodology of using a dual-feedback network for bandwidth extension and dc offset cancellation is analyzed theoretically. The proof of concept is verified by a measured stand-alone VGA chip and it achieves several record performances compared to the existing publications up to date. The chip achieves a 2.2 GHz 3-dB bandwidth with wide tuning range from -10 dB up to 50 dB. Moreover, it consumes only 2.5 mW through a 1 V supply and occupies 0.01 mm2 active area in a standard 90 nm CMOS technology.

A 60-GHz 90-nm CMOS cascode amplifier with interstage matching

The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption

A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna

There is considerable interest in wideband pulse modulation at mm-Wave frequencies for application in radar and medical imaging systems [1,2]. Accuracy and resolution in these respective systems are determined by the minimum pulse width (PW). PWs down to 300ps have previously been reported for 24/79GHz carrier frequencies [1,3]. This paper presents the design of the first pulse-based transmitter with integrated antenna to achieve sub-100ps PWs at mm-Wave frequencies in silicon. The transmitter generates variable measured PWs in the range of 35 to 376ps. To obtain this performance, hybrid PA/antenna switching has been explored in combination with high-speed digital switching circuitry.

Internal Unilaterization Technique for CMOS mm-Wave Amplifiers

An internal unilaterization technique for cas-code devices is analyzed and demonstrated in 90 nm CMOS technology. The substrate network of the device has been incorporated in a circuit technique together with an LC tank on the top gate of the cascode structure. The structure is accurately modeled and conditions for unilaterization of the cascode are derived in terms of the the LC tank parameters. An increase in the maximum stable gain from 7.5 dB to 20 dB has been verified in the measurements using this technique.

A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition

An integrated phase-coherent and pixel-scalable pulsed-radar transceiver with on-chip tapered loop antennas generates programmable pulses down to 36ps using an integrated 94GHz carrier, frequency synthesized and locked to an external reference. A DLL controls the TX pulse position with 2.28ps resolution, which allows the chip to function as a unit element in a timed-array. The receiver also features a >;1.5THz GBW DA as the front-end amplifier, quadrature mixers, and a 26GHz quadrature baseband. Phase coherency allows for ~375μm single-target position resolution by interferometry.