Muhammad M. Mirza

Design and fabrication of memory devices based on nanoscale polyoxometalate clusters

Flash memory devices—that is, non-volatile computer storage media that can be electrically erased and reprogrammed—are vital for portable electronics, but the scaling down of metal–oxide–semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core–shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core–shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(iv)O3)2]4− as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(v)2O6]2− moiety containing a {Se(v)–Se(v)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call ‘write-once-erase’. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching

The development of nanofabrication techniques for creating high aspect ratio (∼50:1) sub-10 nm silicon nanowires (SiNWs) with smooth, uniform, and straight vertical sidewalls using an inductively coupled plasma (ICP) etching process at 20 °C is reported. In particular, to improve the quality and flexibility of the pattern transfer process for high aspect ratio SiNWs, hydrogen silsesquioxane, a high-resolution, inorganic, negative-tone resist for electron-beam lithography has been used as both the resist for defining sub-10 nm patterns and the hard mask for etching the underneath silicon material. The effects of SF6/C4F8 gas flow rates, chamber pressure, platen power and ICP power on the etch rate, selectivity, and sidewall profile are investigated. To minimize plasma-induced sidewall damage, moderate plasma excitation power (ICP power of 600 W) and low ion energy (platen power of 6–12 W) were used. Using the optimized etch process at room temperature (20 °C), the authors have successfully fabricated sub-1...

Determining the electronic performance limitations in top-down-fabricated Si nanowires with mean widths down to 4 nm.

Silicon nanowires have been patterned with mean widths down to 4 nm using top-down lithography and dry etching. Performance-limiting scattering processes have been measured directly which provide new insight into the electronic conduction mechanisms within the nanowires. Results demonstrate a transition from 3-dimensional (3D) to 2D and then 1D as the nanowire mean widths are reduced from 12 to 4 nm. The importance of high quality surface passivation is demonstrated by a lack of significant donor deactivation, resulting in neutral impurity scattering ultimately limiting the electronic performance. The results indicate the important parameters requiring optimization when fabricating nanowires with atomic dimensions.

One dimensional transport in silicon nanowire junction-less field effect transistors

Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.

Germanium on silicon single-photon avalanche detectors using silicon-on-insulator substrates (Conference Presentation)

Single photon avalanche detectors (SPADs) operating in gated-Geiger mode at near infrared wavelengths have applications in quantum key distribution (QKD), eye-safe light detection and ranging (LIDAR), 3D image sensing, quantum enhanced imaging and photonic based quantum information processing. Whilst InGaAs SPADs are commercially available, the high cost and lack of integrated SPADs limit the applications. We have previously demonstrated vertical Geiger mode Ge on Si SPADs at 1310 and 1550 nm operating at 100 K where the Ge is used as an absorber and the lower noise Si is used as the avalanche gain region. At 100 K and 1310 nm a single photon detection efficiency of 4% was demonstrated with a dark count rate (DCR) of 5 MHz. Here we present first results on Ge on Si SPADs grown on top of silicon-on-insulator (SOI) substrates. Both vertical photodetectors and waveguide coupled detectors were investigated with designs aimed to reduce the DCR over previous results. Waveguides and avalanche regions were patterned in the top Si of a SOI wafer before being coated with silicon dioxide. Holes were then etched in the oxide to allow selective area growth of Ge inside these windows and on top of the Si waveguides for the waveguide coupled Ge SPADs. This approach reduces the threading dislocation density compared to bulk Ge growths which aids the reduction of the DCR. The fabricated devices have been tested at both 1310 nm and 1550 nm wavelengths and demonstrate improved performance over previous published results.

Experimental and simulation study of a high current 1D silicon nanowire transistor using heavily doped channels

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories.

Silicon nanowire devices with widths below 5 nm

This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, low-damage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature.

Scaling resonant tunnelling diodes and nanowires using SPICE modelling to optimise nanoscale performance

A simple geometric SPICE model has been developed to evaluate the effects of sidewall charge related current and depletion on the current-voltage characteristics of nanoscale resonant tunneling diodes (RTDs) and Si nanowires. The model confirms that sidewall current is the limiting mechanism for high performance nanoscale RTDs. The model can be developed to fully study the little understood parasitic currents in RTDs and nanowire devices where such currents potentially limit sensitivity. The model is used to analyse Si/SiGe and InGaAs based RTDs and Si nanowires down to 30 nm diameter RTDs and sub-10 nm Si nanowires.