Zul Atfyi Fauzan Mohammed Napiah

Hybrid RSM-fuzzy modeling for hardness prediction of TiAlN coatings

In this paper, a new approach in predicting the hardness of Titanium Aluminum Nitrite (TiAlN) coatings using hybrid RSM-fuzzy model is implemented. TiAlN coatings are usually used in high-speed machining due to its excellent surface hardness and wear resistance. The TiAlN coatings were produced using Physical Vapor Deposition (PVD) magnetron sputtering process. A statistical design of experiment called Response Surface Methodology (RSM) was used in collecting optimized data. The fuzzy rules were constructed using actual experimental data. Meanwhile, the hardness values were generated using the RSM hardness model. Triangular shape of membership functions were used for inputs as well as output. The substrate sputtering power, bias voltage and temperature were selected as the input parameters and the coating hardness as an output of the process. The results of hybrid RSM-fuzzy model were compared against the experimental result and fuzzy single model based on the percentage error, mean square error (MSE), co-efficient determination (R2) and model accuracy. The result indicated that the hybrid RSM-fuzzy model obtained the better result compared to the fuzzy single model. The hybrid model with seven triangular membership functions gave an excellent result with respective average percentage error, MSE, R2 and model accuracy were 11.5%, 1.09, 0.989 and 88.49%. The good performance of the hybrid model showed that the RSM hardness model could be embedded in fuzzy rule-based model to assist in generating more fuzzy rules in order to obtain better prediction result.

NMOS Performance of Low Boron Activation on Group V for Ultra-Shallow Junction Formation

Fabrication of ultra shallow junctions with low contact resistances is desired to advance current CMOS technology. The low Boron activation on Group V for ultra shallow junction formation will makes the chip fabrication works effectively. SilvacoTCAD (Technology Computer Aided Design) manages simulation tasks and analyzing simulation results when ultra-shallow junction formation is using low-boron activation on Phosphorus, Antimony and Arsenic.A stimulate process like implantation, diffusion and dopant activation and epitaxial growth in different semiconductor materials has been analyzed as well as investigate the effects of energy of boron ion beams on ultra shallow junction formation.As a result, the electrical characteristics of NMOS structure by obtaining graph of ID VGS and ID VDShas been studied when there are variations in junction length (Xj), and gatelength (Lg).

Characterization analysis of a novel approach in fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket

The process of making novel CMOS compatible vertical MOSFET by incorporating Dielectric Pocket (DP) is shown using virtual wafer simulation tool. The corresponding device doping profiles of a junction is highlighted and demonstrated good device profiles for the feasibility of the approach. The effect of amorph Si recrystallization as the result of different RTA time is also evaluated. Both the transfer and output characteristics of the DP vertical MOSFETs indicates a reasonable value of drive and off -leakage current (ION and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The increasing time of RTA to 100 s shows better performance of the device than for shorter time, but in the thread-off of higher drain junction depth and leakage current.

Process and characterization of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET)

In this paper, we propose a fabrication process of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET). By employing TCAD tools, a systematic process simulation in realizing the SDP-MOSFET structure is done successfully. By using vertical and horizontal doping profiles, 120 nm gate length with 12 nm gate oxide of the device is observed respectively. The combination of a Silicon Germanium (SiGe) layer and incorporation of dielectric pocket (DP) shows an improved in suppression of short channel effects (SCE) and allows the threshold voltage and the performance of the devices to be optimized. A low leakage current (IOFF), good drive current (ION), higher mobility and lower power consumption are obtained in SDP-MOSFET. Consequently, the threshold voltage (VT) is decreased accordingly in SDP-MOSFET devices and shows a better control of VT roll-off.

A pixel matching process and multiple ROI for stereo images in stereo vision application

This paper presents an analysis of stereo images for an application of stereo vision application. The matching process is to determine the difference of intensities of pixel between stereo images while the region of interest ROI works as a reference area to the stereo vision application. This region is a reference view of the stereo camera and stereo vision baseline is based on horizontal configuration. The block matching technique is briefly described with the performance of its output. The disparity mapping is generated by the algorithm with the reference to the left image coordinate. The algorithm uses Sum of Absolute Differences (SAD) which is developed using Matlab software. The rectification and block matching processes are also briefly described in this paper.

Investigation of short channel immunity of fully depleted double gate MOS with vertical structure

The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.