Muthumanickam Sankarapandian

Preparation and structure of porous dielectrics by plasma enhanced chemical vapor deposition

The preparation of ultralow dielectric constant porous silicon, carbon, oxygen, hydrogen alloy dielectrics, called “pSiCOH,” using a production 200mm plasma enhanced chemical vapor deposition tool and a thermal treatment is reported here. The effect of deposition temperature on the pSiCOH film is examined using Fourier transform infrared (FTIR) spectroscopy, dielectric constant (k), and film shrinkage measurements. For all deposition temperatures, carbon in the final porous film is shown to be predominantly Si–CH3 species, and lower k is shown to correlate with increased concentration of Si–CH3. NMR and FTIR spectroscopies clearly detect the loss of a removable, unstable, hydrocarbon (CHx) phase during the thermal treatment. Also detected are increased cross-linking of the Si–O skeleton, and concentration changes for three distinct structures of carbon. In the as deposited films, deposition temperature also affects the hydrocarbon (CHx) content and the presence of CO and CC functional groups.

Property modifications of nanoporous pSiCOH dielectrics to enhance resistance to plasma-induced damage

The resistance to plasma-induced damage of various nanoporous, ultra low-κ porous SiCOH films used as interconnect dielectric materials in integrated circuits was studied. These films are susceptible to damage by plasma processes used during nanofabrication. The dielectric constants and chemical compositions of four dielectric films were correlated with measured amounts of plasma damage. Films deposited with higher carbon content in the form of Si–CH3 and Si(CH3)2 bonding exhibited less plasma damage than similar films with lower carbon content.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

We report FDSOI devices with a 20nm gate length (L_G) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V_dd of 0.75V, competitive effective current (I_eff) reaches 550/340 μA/μm for NFET, at I_off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V_dd of 0.75V, PFET I_eff reaches 495/260 μA/μm, at I_off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

Nanoporous Materials Integration Into Advanced Microprocessors

Future microprocessor technologies will require interlayer dielectric (ILD) materials with a dielectric constant (κ-value) less than 2.5. Organosilicate glass (OSG) materials must be nanoporous to meet this demand. However, the introduction of nanopores creates many integration challenges. These challenges include 1) integrating nanoporous films with low mechanical strength into conventional process flows, 2) managing etch profiles, 3) processinduced damage to the nanoporous ILD, and 4) controlling the metal/nanoporous ILD interface. This paper reviews research to maximize mechanical strength by engineering optimal pore structures, controlling trench bottom roughness induced by etching and understanding its relationship to pore size, repairing plasma damage using silylation chemistry, and sealing a nanoporous surface for barrier metal (liner) deposition.