Myung-Dong Ko

High efficiency silicon solar cell based on asymmetric nanowire

Improving the efficiency of solar cells through novel materials and devices is critical to realize the full potential of solar energy to meet the growing worldwide energy demands. We present here a highly efficient radial p-n junction silicon solar cell using an asymmetric nanowire structure with a shorter bottom core diameter than at the top. A maximum short circuit current density of 27.5 mA/cm2 and an efficiency of 7.53% were realized without anti-reflection coating. Changing the silicon nanowire (SiNW) structure from conventional symmetric to asymmetric nature improves the efficiency due to increased short circuit current density. From numerical simulation and measurement of the optical characteristics, the total reflection on the sidewalls is seen to increase the light trapping path and charge carrier generation in the radial junction of the asymmetric SiNW, yielding high external quantum efficiency and short circuit current density. The proposed asymmetric structure has great potential to effectively improve the efficiency of the SiNW solar cells.

Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis

A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poissons equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Investigation of Low-Frequency Noise Behavior After Hot-Carrier Stress in an n-Channel Junctionless Nanowire MOSFET

The dc performance and low-frequency (LF) noise behaviors after hot-carrier (HC)-induced stress were compared for a junctionless nanowire transistor (JNT) and an inversion-mode nanowire transistor (INT). Less dc degradation was found in the JNT than in the INT. Due to the low lateral peak electric field (E-field) and electrons traveling through the center of the nanowire, the LF noise increment after HC-induced stress in the JNT is much lower than that in the INT. Furthermore, due to the higher lateral peak E-field located under the gate and the conduction path that occurs near the surface, the LF noise of the INT is very sensitive to HC stress.

Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration

We performed 3D simulations to demonstrate structural effects in sub-20 nm gate-all-around silicon nanowire field effect transistors having asymmetric channel width along the channel direction. We analyzed the differences in the electrical and physical properties for various slopes of the channel width in asymmetric silicon nanowire field effect transistors (SNWFETs) and compared them to symmetrical SNWFETs with uniform channel width. In the same manner, the effects of the individual doping concentration at the source and drain also have been investigated. For various structural conditions, the current and switching characteristics are seriously affected. The differences attributed to the doping levels and geometric conditions are due to the electric field and electron density profile.

Comparative study of fabricated junctionless and inversion-mode nanowire FETs

For the higher degree of integration and better performance of a device, the feature size of conventional MOSFET is expected to go down under 20 nm within a few years [1] and the nanowire FET (NWFET) is the most conspicuous candidate for the future device application. However, in the case of conventional inversion mode NWFETs (cINT), the formation of an abrupt junction for the source/drain (SD) is one of the technical obstacles [2]. Recently, junctionless NWFETs (JNT) where the channel and SD region are doped with the same dopant type has been suggested [3]. In this work, the n-type JNTs and cINT are fabricated with the gate length (LG) of 20 ∼ 250 nm and compared their electrical DC characteristics and low-frequency noise characteristics.

Optical and electrical characteristics of asymmetric nanowire solar cells

We propose an asymmetric radial structure developed via simulation that improves the optical and electrical characteristics of silicon nanowire (SiNW) solar cells. This nanostructure is designed by shrinking the bottom core diameter and holding the top core diameter fixed in the SiNW, which results in a total reflection of the incident light in the outer wall of the shell due to the difference in the refractive index. The reflection enhances light trapping and concentration, which results in a 10 times higher optical generation rate and greater optical absorption in the high energy regime as compared with the fundamental symmetric radial structure. Further, we found that the efficiency is increased by over 10% when the bottom core diameter is decreased. The proposed structure has great potential to effectively improve the efficiency in concert with optimizing the design parameters.

Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

This work investigates the effect of Hfin on the device and circuit characteristics, and discusses the design aspects for the SoC integration such as 6T-SRAM and 2-stage OPAMPs. Table summarizes the device- and circuit-level assessment using the FinFETs and the planar FETs. Even though the gate control of FinFETs is better than of the planar FETs, further attention should be paid to design Hfin of the FinFETs. SoC blocks such as SRAMs require both high density and low power, so the minimum Lgate will restrict designing Hfin. On the other hand, the analog/RF applications prefer long Lgate to achieve high output resistance for better performance, so we may raise the Hfin without losing the gate control capability. Multiple Hfin design may be good choice for the sub-22-nm SoC integration because Hfin may affect the power, density, and the design convenience.

Investigation on hot carrier effects in n-type short-channel junctionless nanowire transistors

Hot carrier induced degradation of the n-type junctionless nanowire transistor (JNT) and the inversion-mode NWFET (IMNT) has been experimentally compared. The JNT shows better hot carrier (HC) immunity than the IMNT. The lateral peak electrical field intensity is lower in the JNT than the IMNT, which is observed by TCAD simulation work.

Extraction of series resistance on junctionless and inversion-mode nanowire FET through the method based on Y-function

In the devices with nanowire channel, series resistance is an important parameter. As the channel length is scaled down, channel resistance is gradually small and it has therefore become an important issue to keep the value of series resistance smaller than channel resistance in order to ensure the device performance. Moreover, the series resistance fluctuates in the devices; it is mainly due to its three dimensional contact configuration between the source/drain and channel. Due to these reasons, therefore, it is important to extract the series resistance and to examine its behavior in terms of appropriate device parameters and the complexity of contact configuration. Recently, the junctionless nanowire transistor (JNT) is spotlighted due to its high on/off ratio, excellent gate controllability through multiple-gate structure, the immunity of short channel effect such as DIBL and threshold voltage roll-off, and the extremely simple fabrication process. Although many studies have been carried out for the JNT, the research on the comparative analysis of the series resistance of between the JNT and the inversion mode nanowire FET was not performed yet. In this paper, we demonstrated and compared the extracted series resistance between fabricated JNTs and inversion mode nanowire FET (IMN-FET) through the method based on Y-function. This technique provides to extract the series resistance of both devices obviously and accurately. The observed data are discussed based on the existing theories.