Chan-Hoon Park

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Fin Width and Bias Dependence of the Response of Triple-Gate MOSFETs to Total Dose Irradiation

The total ionizing dose response of triple-gate MOSFETs is investigated for various fin widths and bias conditions. Experiments and simulations are used to analyze the buildup of trapped charge in the buried oxide and its impact on the threshold-voltage shift and subthreshold-slope degradation. The higher total-dose tolerance of multiple-gate FinFETs with narrow fins is attributed to lateral gate control over the electrostatic potential in the body and especially at the Si fin/BOX interface. It is demonstrated that ON-state irradiation is the worst-case bias configuration for triple-gate MOSFETs through extensive experimental analysis.

Investigation of Low-Frequency Noise Behavior After Hot-Carrier Stress in an n-Channel Junctionless Nanowire MOSFET

The dc performance and low-frequency (LF) noise behaviors after hot-carrier (HC)-induced stress were compared for a junctionless nanowire transistor (JNT) and an inversion-mode nanowire transistor (INT). Less dc degradation was found in the JNT than in the INT. Due to the low lateral peak electric field (E-field) and electrons traveling through the center of the nanowire, the LF noise increment after HC-induced stress in the JNT is much lower than that in the INT. Furthermore, due to the higher lateral peak E-field located under the gate and the conduction path that occurs near the surface, the LF noise of the INT is very sensitive to HC stress.

Comparative study of fabricated junctionless and inversion-mode nanowire FETs

For the higher degree of integration and better performance of a device, the feature size of conventional MOSFET is expected to go down under 20 nm within a few years [1] and the nanowire FET (NWFET) is the most conspicuous candidate for the future device application. However, in the case of conventional inversion mode NWFETs (cINT), the formation of an abrupt junction for the source/drain (SD) is one of the technical obstacles [2]. Recently, junctionless NWFETs (JNT) where the channel and SD region are doped with the same dopant type has been suggested [3]. In this work, the n-type JNTs and cINT are fabricated with the gate length (LG) of 20 ∼ 250 nm and compared their electrical DC characteristics and low-frequency noise characteristics.

Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

This work investigates the effect of Hfin on the device and circuit characteristics, and discusses the design aspects for the SoC integration such as 6T-SRAM and 2-stage OPAMPs. Table summarizes the device- and circuit-level assessment using the FinFETs and the planar FETs. Even though the gate control of FinFETs is better than of the planar FETs, further attention should be paid to design Hfin of the FinFETs. SoC blocks such as SRAMs require both high density and low power, so the minimum Lgate will restrict designing Hfin. On the other hand, the analog/RF applications prefer long Lgate to achieve high output resistance for better performance, so we may raise the Hfin without losing the gate control capability. Multiple Hfin design may be good choice for the sub-22-nm SoC integration because Hfin may affect the power, density, and the design convenience.

Investigation on hot carrier effects in n-type short-channel junctionless nanowire transistors

Hot carrier induced degradation of the n-type junctionless nanowire transistor (JNT) and the inversion-mode NWFET (IMNT) has been experimentally compared. The JNT shows better hot carrier (HC) immunity than the IMNT. The lateral peak electrical field intensity is lower in the JNT than the IMNT, which is observed by TCAD simulation work.

Characterization of Gate-All-Around Si-NWFET, including R sd , cylindrical coordinate based 1/f noise and hot carrier effects

In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, Sid, for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.

Fabrication and characterization of gate-all-around silicon nanowire field effect transistors

In this paper, we show the junctionless nanowire FETs (JNTs) with gate length of 20 nm and the conventional inversion mode nanowire FETs (cINTs). The fabricated JNT has shown better electrical characteristics with high Ion / Ioff ratio (>106) and subthreshold slope (∼75 mV/dec) than cINT, which means that the simpler fabrication process without junction formation makes the JNT a promising candidate for the next generation CMOS technology node. The nano-scale three dimensional and radial shaped structures lead to more oxide and interface traps and 1-D or 3-D configurations between the channel and source/drain. Consequently, drain current fluctuation, channel and series resistances become dominant parameters in estimating the performance of nanowire FETs (NWFETs) as the channel length is scaled down. Here, we report more reliable extraction of Rsd with other device parameters such as effective mobility, threshold voltage by the Y-function method, and volume trap density by the flicker noise analysis. In addition, radius dependence of flicker noise is discussed.

pH sensing and noise characteristics of Si nanowire ion-sensitive field effect transistors

We have fabricated Si-nanowire (Si-NW) based ion-sensitive field effect transistors (ISFETSs) for biosensing applications. The ability to prepare a large number of sensors on a wafer, standard silicon microfabrication techniques resulting in cost savings and potential sensitivity are significant advantages in favor of nanoscale ISFETs for future biosensor requirements. The Si-NW ISFETs were produced using a combination of oxide-grown Si-NWs and integrated Ag/AgCl reference electrodes. The Si-NWs were fabricated on a standard silicon-on-insulator wafer using electron-beam lithography and conventional semiconductor processing techniques. To form an Ag/AgCl reference electrode, a 250-nm thick Ag layer was deposited and later chlorinated in 100 mM KCl solution. SEM analysis reveals Si-NWs with a width of ∼50 nm and a length of 10 µm. The DC characteristics were measured by placing an ISFET with 100 Si-NWs in parallel in a 0.1× PBS buffer solution. The measured ID-VG characteristics show an n-type FET behavior with a relatively high on/off current ratio, reasonable sub-threshold swing value, and low gate-leakage current. The pH responses of the ISFETs with different pH solutions were characterized at room temperature. A lateral shift of the ID-VG curve is clearly observed by changing the pH value of the solution. The low frequency noise characteristics have been performed in order to evaluate interface quality of the devices.

Investigation on physical origins of endurance failures in PRAM

Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic transport and for better cycling performance was proposed.