N. A. Hastas

High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices

High mobility thin‐film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin‐film transistors is reported that exploits the enhanced electron transport properties of low‐dimensional polycrystalline heterojunctions and quasi‐superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band‐like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature‐dependent electron transport and capacitance‐voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas‐like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll‐to‐roll, etc.) and can be seen as an extremely promising technology for application in next‐generation large area optoelectronics such as ultrahigh definition optical displays and large‐area microelectronics where high performance is a key requirement.

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

A fully analytical surface-potential-based drain current model for amorphous InGaZnO (α-IGZO) thin film transistors (TFTs) has been developed based on a Gaussian distribution of subgap states, with the central energy fixed at the conduction band edge, which is approximated by two exponential distributions. This model includes both drift and diffusion components to describe the drain current in all regions of operation. Using an empirical mobility relationship that depends on both horizontal and vertical electric field, it is demonstrated that the model describes accurately the experimental transfer and output characteristics, making the model suitable for the design of circuits using α-IGZO TFTs.

Effects of buffer layer properties and annealing process on bulk heterojunction morphology and organic solar cell performance

The performance of polymer–fullerene bulk heterojunction (BHJ) solar cells is strongly dependent on the vertical distribution of the donor and acceptor regions within the BHJ layer. In this work, we investigate in detail the effect of the hole transport layer (HTL) physical properties and the thermal annealing on the BHJ morphology and the solar cell performance. For this purpose, we have prepared solar cells with four distinct formulations of poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) buffer layers. The samples were subjected to thermal annealing, applied either before (pre-annealing) or after (post-annealing) the cathode metal deposition. The effect of the HTL and the annealing process on the BHJ ingredient distribution – namely, poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl C61 butyric acid methyl ester (PCBM) – has been studied by spectroscopic ellipsometry and atomic force microscopy. The results revealed P3HT segregation at the top region of the films, which had a detrimental effect on all pre-annealed devices, whereas PCBM was found to accumulate at the bottom interface. This demixing process depends on the PEDOT:PSS surface energy; the more hydrophilic the surface the more profound is the vertical phase separation within the BHJ. At the same time those samples suffer from high recombination losses as evident from the analysis of the J–V measurements obtained in the dark. Our results underline the significant effect of the HTL–active and active–ETL (electron transport layer) interfacial composition that should be taken into account during the optimization of all polymer–fullerene solar cells.

Low frequency noise of GaAs Schottky diodes with embedded InAs quantum layer and self-assembled quantum dots

The electrical properties of InAs quantum layer (QL) and self-assembled quantum-dots (QDs), embedded in GaAs, are investigated by low-frequency noise measurements using Au/n-GaAs Schottky diodes as test devices. The measurements are carried out in the forward conduction regime with forward current IF as a parameter. Current–voltage and capacitance–voltage measurements indicate that GaAs and GaAs/InAs-QL Schottky diodes are nearly ideal, even though defects are present in the space–charge region of GaAs/InAs-QD Schottky diodes. In GaAs and GaAs/InAs-QL Schottky diodes, the power spectral density of the current fluctuations, S1, shows 1/f behavior and is proportional to IF2, which is explained by modulation of the barrier height due to trapping and detrapping phenomena. In GaAs/InAs-QD Schottky diodes, S1 shows 1/fγ (with γ≈0.6) behavior and is proportional to IF2 in the low current region and proportional to IF2.5 in the high current region. These noise data are explained by the generation of band tail sta...

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Abstract Experimental investigation of the substrate current Isub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, Isub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, Isub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.

Microstructure and its effect on the conductivity of magnetron sputtered carbon thin films

Carbon thin films were grown by magnetron sputtering at room temperature on silicon substrates, with the substrate bias voltage varying from +10 to −200 V. Transmission electron microscopy analysis has shown that films deposited at Vb=+10 and −40 V are amorphous (α-C), while films deposited at Vb=−200 V are nanocrystalline (nc-C). Temperature dependent conductivity measurements were carried out in the temperature range 300–77 K. With respect to conductivity, the results indicate that the investigated carbon films are classified in three groups: (i) In α-C films deposited at Vb=+10 V (sp2 rich bonds), the variable range hopping (VRH) conduction dominates below 300 K. (ii) In α-C films deposited at negative Vb up to −100 V (sp3 rich bonds), VRH conduction dominates at low temperatures (T 150 K). (iii) In nc-C film deposited at Vb=−200 V, the conductivity is explained by a heteroquantum-dots model based on a t...

Investigation of single electron traps induced by InAs quantum dots embedded in GaAs layer using the low-frequency noise technique

The properties of the traps induced by InAs quantum dots (QDs), embedded in a GaAs layer grown by molecular beam epitaxy, are investigated by the low-frequency noise measurements using the Au∕n-GaAs Schottky diode as a test device. The forward current noise spectra are composed of two noise components: a 1∕f-like noise at low frequencies and a generation-recombination (g-r) noise at higher frequencies. The 1∕f noise is ascribed to the mobility fluctuations within the space-charge region. The obtained Hooge parameter (αH=6×10−5) is larger than the expected value considering the phonon or impurity scattering mechanism, indicating the presence of the defects associated with QDs. The analysis of the g-r noise gives a single trap of density of about 1.6×1014cm−3 in the part of the GaAs layer located above the QDs.

Structural, electrical, and low-frequency-noise properties of amorphous-carbon–silicon heterojunctions

The structural, electrical, and low-frequency-noise properties of heterojunctions of amor- phous-carbon (a-C) films grown on either n- or p-type single-crystal silicon are investigated. The a-C films were deposited by rf magnetron sputtering at room temperature with varying the substrate bias Vb, from +10 to −200 V. The study includes measurements of x-ray reflectivity (XRR), low-frequency noise at room temperature, and dark current–voltage (I–V) and capacitance–voltage (C–V) characteristics over a wide temperature range. Analysis of the XRR data indicates the presence of a thin SiC layer between a-C and Si, with thickness increasing up to about 1.8 nm for Vb=−200 V. The results show that the noise properties of the devices are independent of the SiC interlayer and the a-C film deposition conditions, while the noise of the a-C/n-Si heterojunctions is about four orders of magnitude lower than that of the a-C/p-Si heterojunctions. Analysis of the I–V and C–V data shows that the rectification properties of t...

An analytical hot-carrier induced degradation model in polysilicon TFTs

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.