D. H. Tassis

Determination of bulk states and interface states distributions in polycrystalline silicon thin‐film transistors

The field‐effect conductance activation energy Ea as a function of the gate voltage Vg is investigated for polycrystalline silicon thin‐film transistors. An analytical expression for Ea is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental Ea vs Vg data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin‐film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

On the threshold voltage and channel conductance of polycrystalline silicon thin‐film transistors

A model for the grain‐boundary barrier height of undoped polycrystalline silicon thin‐film transistors is developed based on a rodlike structure of the grains with a square cross section and a Gaussian energy distribution of the trapping states at the grain boundaries. An analytical expression for the threshold voltage is derived in terms of the distribution parameters of the grain‐boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters affecting the threshold voltage and the channel conductance of the transistor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation of the grain‐boundary trapping states, the increase of the grain size and mainly the scaling down of the gate o...

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage models are compared with the Atlas simulation results, with variables being the device dimensions, the interface-charge region length and the interface-charge density. A good agreement between the model and simulation results has been observed by calibrating as a constant parameter the gate voltage included in the position of the minimum potential and the carrier charge-sheet density at the potential minimum that is adequate to achieve the turn-on condition.

A compact drain current model of short-channel cylindrical gate-all-around MOSFETs

A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.

Infrared spectroscopic and electronic transport properties of polycrystalline semiconducting FeSi2 thin films

Polycrystalline semiconducting FeSi2 thin films were grown on (100) Si substrates of high resistivity by electron beam evaporation of amorphous Si/Fe ultrathin multilayers in an ultrahigh vacuum system, followed by conventional vacuum furnace (CF) or rapid thermal annealing (RTA). Infrared reflectance and transmittance measurements were employed for optical characterization of the samples at room temperature. The results indicate a direct transition at about 0.85 eV, an indirect transition at about 0.79 eV, and exponential band tail states within the band gap. The quality of the silicide is improved by increasing the annealing temperature from 600 to 800 °C in the RTA process, while the opposite is observed in the CF annealed samples. Transport measurements were performed on a typical β‐FeSi2 layer of high quality grown by CF at low temperature. The measured mobility is about 97 cm2/V s and the hole concentration is about 1×1017 cm−3. The mobility is a factor of 10 higher and the hole concentration a fact...

Characteristics of TiNx/n-Si Schottky diodes deposited by reactive magnetron sputtering

The effects of the substrate bias voltage and the deposition temperature on the electrical characteristics and the 1/f noise of TiNx/n-Si Schottky diodes fabricated by reactive magnetron sputtering are investigated. As the substrate bias voltage varies from −40 to −100 V, the ideality factor of the diodes remain almost unchanged whereas the noise intensity as a function of the current shows a shift parallel by about one order of magnitude. At low current levels, the noise intensity is proportional to the current and is attributed to the mobility and diffusivity fluctuation. At higher current levels, the noise intensity is proportional to the square of the current and is attributed to bulk traps mainly near the interface. Analysis of the noise measurements shows that both the Hooge parameter and the bulk trap density near the interface first are increased and then decreased as the negative substrate bias voltage increases from −40 to −100 V. This is in contrast with the effects of the deposition temperatur...

Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

The Meyer–Neldel rule in the conductivity of polycrystalline semiconducting FeSi2 films

The electrical transport properties of polycrystalline semiconducting β-FeSi2 films have been evaluated by conductivity (σ) measurements over the temperature range 50–300 K. At low temperatures (T<200 K), a variable range hopping conduction was observed, from which the number of states near the Fermi level and the degree of disorder in the material were obtained. At moderate temperatures (200–300 K), the ln σ vs 103/T curves show anomalous features such as kinks or continuous bending. In this temperature range, the conductivity data satisfy the Meyer–Neldel rule, (MNR), which is of fundamental importance for the transport properties of the β-FeSi2. The results show that the MNR parameters are related with the degree of disorder in the material.