N. Arpatzanis

A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation

A simple current-voltage model for polycrystalline silicon thin-film transistors (polysilicon TFTs) is proposed, including the sixth-order polynomial function coefficients fitted to the effective mobility versus gate voltage data, the channel length modulation, and impact ionization effects. The model possesses continuity of current in the transfer characteristics from weak to strong inversion and in the output characteristics throughout the linear and saturation regions of operation. The model parameters are used as input parameters in AIM-SPICE circuit simulator for device modeling. The model has been applied in a number of long and short channel TFTs, and the statistical distributions of the model parameters have been derived which are useful for checking the functionality of TFTs circuits with AIM-SPICE.

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 1012 cm -2 in the upper part of the nc-Si film is reduced to 2.1 times 1012 cm-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen

Analytical current-voltage model for nanocrystalline silicon thin-film transistors

An analytical model for the drain current above threshold voltage, based on an exponential energy distribution of band tail states, has been applied to bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Analysis of the model shows that the slope of the exponential band tails determines the behavior of the device current-voltage characteristics. Comparison with experimental data shows that few fundamental model parameters, related to the material quality and different physical effects, can be used to describe consistently both output and transfer characteristics of nc-Si TFTs over a wide range of channel lengths.

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.

Electrical and noise characterization of bottom-gated nanocrystalline silicon thin-film transistors

Bottom-gated n-channel thin-film transistors were fabricated on nanocrystalline silicon (nc-Si) layers, deposited at 230°C by plasma-enhanced chemical vapor deposition. The transfer characteristics were measured in devices with different channel dimensions, exhibiting front and back channel conduction. The change of the device parameters with channel dimensions is explained in terms of the trap density in the bulk of the nc-Si layer extracted from space charge limited current measurements in n+‐nc‐Si‐n+ structures and both front∕back interface traps determined from the slopes associated with the front and back channel conduction. The overall results suggest the existence of regions of high trap density at the back interface near the source and drain n+ contacts, whereas the reduction of the back channel conduction with decreasing the channel width can be attributed to the sidewall edge effect. The gate insulator trap concentration of 1.5×1019cm−3eV−1 was deduced from the noise data.

Effect of Channel Width on the Electrical Characteristics of Amorphous/Nanocrystalline Silicon Bilayer Thin-Film Transistors

The effect of the channel width dimension on the electrical characteristics of amorphous/nanocrystalline silicon bilayer thin-film transistors (TFTs) is investigated. For comparison, nanocrystalline silicon monolayer TFTs are also studied. The experimental results show that the leakage current is decreased and the back-channel conduction is suppressed in bilayer channel devices. The overall results demonstrate that the performance of bilayer TFTs is enhanced with decreasing the channel width, which is attributed to the corner effect

Effect of rapid thermal annealing on the noise properties of InAs/GaAs quantum dot structures

Self-assembled InAs quantum dots (QDs) were grown by molecular beam epitaxy (MBE) on n+‐GaAs substrates, capped between 0.4μm thick n-type GaAs layers with electron concentration of 1×1016cm−3. The effect of rapid thermal annealing at 700°C for 60s on the noise properties of the structure has been investigated using Au∕n‐GaAs Schottky diodes as test devices. In the reference sample without containing QDs, the noise spectra show a generation-recombination (g-r) noise behavior due to a discrete energy level located about 0.51eV below the conduction band edge. This trap is ascribed to the M4 (or EL3) trap in GaAs MBE layers, related to a chemical impurity-native defect complex. In the structure with embedded QDs, the observed g-r noise spectra are due to a midgap trap level ascribed to the EL2 trap in GaAs, which is related to the InAs QDs dissolution due to the thermal treatment.

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.

Current–voltage and noise characteristics of reverse-biased Au/n-GaAs Schottky diodes with embedded InAs quantum dots

Schottky contacts on n-type GaAs with embedded InAs quantum dots (QDs) were studied by current–voltage (I–V) and low-frequency noise measurements. For comparison, diodes not containing QDs were investigated as reference devices. A wide distribution of the ideality factor was observed, correlated with the level of the leakage current. Reverse I–V characteristics on the logarithmic scale indicate that the space-charge limited current dominates the carrier transport in these diodes. In all diodes, the reverse current noise spectra show 1/f behaviour, attributed to traps uniformly distributed in energy within the band-gap of the GaAs capping layer. Depth profiling measurements of the 1/f noise power spectral density demonstrate the impact of the QDs on these traps. In diodes containing QDs, in addition to the 1/f noise, a generation–recombination noise is found originating from a deep trap level localized in the vicinity of the QD plane.

Hysteresis effect in bottom-gate polymorphous silicon thin-film transistors

The hysteresis effect observed in the transfer characteristics of n-channel bottom-gate hydrogenated polymorphous silicon (pm-Si:H) thin-film transistors (TFTs) is investigated in terms of the channel width. Such phenomenon is observed in devices of wide channel (>20 μm), whereas it diminishes in devices of narrow channel. The hysteresis of wide channel TFTs is mainly due to charges injected from the channel, trapped in the gate dielectric. As the channel width is reduced the edge effect becomes more significant and the effect of carrier injection from the channel is eliminated, which is balanced by the effect of charge injection from the gate electrode.