C.A. Dimitriadis

On-current modeling of large-grain polycrystalline silicon thin-film transistors

Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 /spl mu/m), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K. Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained.

A Fast and Compact Analog Buffer Design for Active Matrix Liquid Crystal Displays Using Polysilicon Thin-Film Transistors

This paper presents a new source-follower type analog buffer for active-matrix liquid crystal displays applications, which exhibits high immunity to the threshold voltage variations of the polysilicon (poly-Si) thin-film transistors (TFTs). The functionality of the buffer was verified through simulations. In order for the simulations to be realistic, parameters extraction from fabricated poly-Si TFTs were used.

A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays

In this paper, a new source-follower-type analog buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed. The buffer, consisting of five n-type polysilicon TFTs, one bias voltage, and an additional control signal, exhibits high immunity to threshold voltage and mobility variations. The functionality of the proposed buffer was verified by HSPICE simulations. In order to obtain realistic simulations, the TFT model parameters used for the simulations were extracted from fabricated TFTs using the Silvaco tools (ATLAS). The proposed buffer has 7-bit output voltage with the dynamic output voltage range of 7.5 V ranging from 2.5 to 10 V and with resolution up to 0.03 V

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with W_fin = 10 nm, measured at V_d = 0.03 V after HC stress at V_stress = 1.8 V for different stress times. The degradation of the device parameters V_t, η and on-state drain current is clearly observed. The positive V_t shift indicates the built-up of a negative charge in the gate dielectric. The negative charge can result either from electron trapping in the gate dielectric or from generation of acceptor-type interface traps. Figure 1(b) shows the transconductance g_m degradation during HC stress. Degradation of the maximum g_m is observed attributed to the interface degradation, with a simultaneous parallel g_m shift due to charge injection into the gate dielectric bulk defects [4]. Using the relation SS=(kT/q).qD_it/C_ox for the subthreshold slope SS, where C_ox is the gate oxide capacitance and kT is the thermal energy, from figure 1(a) the extracted interface trap density D_it changes from 4×10¹² to 5.5×10¹²cm^-2eV^-1.

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

Active-Matrix Liquid Crystal Displays - Operation, Electronics and Analog Circuits Design

For more than four decades, Cathode Ray Tube (CRT) Displays have been the dominant display technology providing very attractive performance. Brightness, contrast ratio, high image quality, speed and resolution were the main high standard specifications that CRTs were satisfied. The last two decades, there was a tremendous growth in small portable applications which required the necessary adjustment of the display technology to them. The large depth of the CRTs was the main disadvantage for preventing them to be used in these kinds of applications. Flat Panel Displays seem to be the most attractive solution to this problem. Displays engineers searched for many years in order to find the suitable flat panel display technologies that could replace CRT displays. The first successfully established flat panel technology was the plasma displays, which demonstrated to be of larger size and higher image quality compared to the CRT technology. However, the problem with the integration of plasma displays in small portable applications still exists. Finally, the inroad of the thinfilm transistors liquid crystal displays (TFT-LCD), in late 1990’s, was a milestone in the displays industry and technology. The successful development of the TFT-LCDs was achieved not accidentally. It was the sequence of the liquid crystal cell technology development, in combination with the development of semiconductors technologies for large-area microelectronics on glass, like thin-film transistors. Although, both technologies were very-well known before the 90’s, an extended research for establishing compatible fabrication processes for the materials and the manufacturing equipment has led to the TFT-LCDs realization. TFT-LCDs were rapidly grown and dominated the displays industry, especially in small portable applications. The implementation of the TFT-LCD panel peripheral driving components with low-power CMOS blocks and, therefore, the compatibility with battery operation was the main reason for the ascendance of the TFT-LCD technology in small portable applications. Today, the TFT-LCD market has been expanded. They can be used in an extremely wide range of our everyday life products, like mobile phone applications, ATMs, PDAs, navigation systems, notebook PCs and home applications, such as wide screen TVs. O pe n A cc es s D at ab as e w w w .in te ch w eb .o rg

Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs

In this work the impact of the source - drain series resistance mismatch on the drain current variability has been investigated for 28nm Bulk MOSFETs. For the first time a mismatch model including the local fluctuations of the threshold voltage, the current gain factor and the source - drain series resistance both in linear and saturation region is presented. Furthermore, it is proved that the influence of source - drain series resistance mismatch is attenuated at the saturation region, due to lower drain current sensitivity to series resistance variation. The experimental results were further verified by Monte Carlo simulation with normally distributed MOSFET parameters.

Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs

A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.

A comprehensive analysis of nanoscale single- and multi-gate MOSFETs

Analog/RF performance of nanoscale triple gate FinFETs and planar single-gate (SG) and double-gate (DG) SOI MOSFETs is examined via extensive 3D device simulations. Well-designed DG MOSFETs attain higher values of cut-off frequency for both lower and higher drain currents, whereas triple-gate (TG) FinFETs offer higher intrinsic gain while compromising cut-off frequency. For longer channel lengths, SG MOSFETs show slightly higher cut-off frequency in comparison to multi-gate (MG) MOSFETs, whereas MG MOSFETs exhibit higher cut-off frequency for lower channel lengths. A unique figure of merit, gain transconductance frequency product (GTFP) for best trade-off among gain, transconductance, and speed is compared. Double-gate MOSFETs exhibit higher GTFP over a wide range of device scaling, thus remain a good candidate for analog/RF applications. Furthermore, the RF linearity performance of these devices has been examined.