A. T. Hatzopoulos

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.

A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation

A simple current-voltage model for polycrystalline silicon thin-film transistors (polysilicon TFTs) is proposed, including the sixth-order polynomial function coefficients fitted to the effective mobility versus gate voltage data, the channel length modulation, and impact ionization effects. The model possesses continuity of current in the transfer characteristics from weak to strong inversion and in the output characteristics throughout the linear and saturation regions of operation. The model parameters are used as input parameters in AIM-SPICE circuit simulator for device modeling. The model has been applied in a number of long and short channel TFTs, and the statistical distributions of the model parameters have been derived which are useful for checking the functionality of TFTs circuits with AIM-SPICE.

An analytical hot-carrier induced degradation model in polysilicon TFTs

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 1012 cm -2 in the upper part of the nc-Si film is reduced to 2.1 times 1012 cm-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen

Analytical current-voltage model for nanocrystalline silicon thin-film transistors

An analytical model for the drain current above threshold voltage, based on an exponential energy distribution of band tail states, has been applied to bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Analysis of the model shows that the slope of the exponential band tails determines the behavior of the device current-voltage characteristics. Comparison with experimental data shows that few fundamental model parameters, related to the material quality and different physical effects, can be used to describe consistently both output and transfer characteristics of nc-Si TFTs over a wide range of channel lengths.

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.

Electrical and noise characterization of bottom-gated nanocrystalline silicon thin-film transistors

Bottom-gated n-channel thin-film transistors were fabricated on nanocrystalline silicon (nc-Si) layers, deposited at 230°C by plasma-enhanced chemical vapor deposition. The transfer characteristics were measured in devices with different channel dimensions, exhibiting front and back channel conduction. The change of the device parameters with channel dimensions is explained in terms of the trap density in the bulk of the nc-Si layer extracted from space charge limited current measurements in n+‐nc‐Si‐n+ structures and both front∕back interface traps determined from the slopes associated with the front and back channel conduction. The overall results suggest the existence of regions of high trap density at the back interface near the source and drain n+ contacts, whereas the reduction of the back channel conduction with decreasing the channel width can be attributed to the sidewall edge effect. The gate insulator trap concentration of 1.5×1019cm−3eV−1 was deduced from the noise data.

Effect of Channel Width on the Electrical Characteristics of Amorphous/Nanocrystalline Silicon Bilayer Thin-Film Transistors

The effect of the channel width dimension on the electrical characteristics of amorphous/nanocrystalline silicon bilayer thin-film transistors (TFTs) is investigated. For comparison, nanocrystalline silicon monolayer TFTs are also studied. The experimental results show that the leakage current is decreased and the back-channel conduction is suppressed in bilayer channel devices. The overall results demonstrate that the performance of bilayer TFTs is enhanced with decreasing the channel width, which is attributed to the corner effect

Analytical on-state current model of polycrystalline silicon thin-film transistors including the kink effect

A simple analytical expression for the on-state current of polycrystalline silicon thin-film transistors is presented, valid in both linear and saturation regimes including the impact ionization effect. The maximum channel electric field and the avalanche multiplication factor are described in terms of an average trapped charge density at the grain boundary, varying with gate voltage due to the continuous energy distribution of the grain boundary trap states. Based on the parameters of the charge inversion voltage, effective carrier mobility and grain boundary barrier height which are extracted from the transfer characteristic at low drain voltage, the model reproduces the experimental output characteristics in devices with different gate lengths using few fitting parameters.

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.