P.A. Martinez

Wien-type oscillators using CCII+

The purpose of this paper is to show that exists a close relationship between some CCII+ based sinusoidal oscillators and the RC active second order oscillators with a single VCVS. These structures with CCII+ may be derived from the classic Wien-bridge oscillator, and four of them exhibit practical interest. They are canonical, the oscillation condition can be adjusted by a single resistor, and furthermore, they may be designed with the same procedure as their voltage amplifier counterparts. Experimental and simulation results supporting the theoretical analysis are given.

An improved Wien bridge oscillator

A type of RC-active Wien-bridge oscillator is proposed whose oscillation frequency is independent of the time constants of the op amps used in the design and is determined only by passive components. Other important effects such as the influence of parasitic poles and nonlinearities in the stability of the system are also analyzed. Experimental results are given, showing close agreement with theoretical predictions. >

Low-Voltage Low-Power CMOS Rail-to-Rail Voltage-to-Current Converters

This paper presents three compact CMOS voltage-to-current converters based on OTA/common-source configurations, which attain rail-to-rail input-output operation. The three converters present a high impedance input node while provide a highly linear V-I relationship over a ( -40, +120°C) temperature range with a maximum transconductance temperature coefficient of 175 ppm/°C. Measurement results for 1.2-V 0.18- μm CMOS implementations confirm rail-to-rail operation with bandwidths of up to 14.5 MHz and THD of up to -50 dB for 1 Vpp at 100 kHz, active areas below 0.0145 μm2 and power consumption below 85 μW, which make these basic building blocks suitable for portable applications.

Designing Adaptive Conditioning Electronics for Smart Sensing

This paper presents a robust digitally programmable CMOS analogue processor designed for sensor output conditioning in embedded applications. In addition, system adaptability allows for correction of the deviations in circuit operation due to ageing, mismatch or environmental effects, lending a smart nature to the devices. In order to tune the free parameters of the system, two training strategies based on perturbative algorithms are compared. The processor performance is validated by adjusting the response of an angular position sensor and the insensitivity to parameter mismatch is demonstrated through high-level simulations based on Monte Carlo electrical simulation data.

1.8 V-100 MHz CMOS programmable gain amplifier

This paper presents a low-voltage low-power differential programmable gain amplifier (PGA) for wideband applications. The proposed cell is based on a gm-boosted source degenerated differential pair with a hybrid polysilicon-MOS resistor degeneration structure. Fabricated in a 0.35 mum CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Measured results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below -72 dB over the whole gain range at 10 MHz for a 0.2 Vp-p differential output

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 μm design supplied at 3.3 V show very low resistance at node X (< 50 Ω), high frequency operation (∼100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/μs.

Impact of bandwidth on contrast sensitive structures for low k1 lithography

Double-patterning ArF immersion lithography continues to advance the patterning resolution and overlay requirements and has enabled the continuation of semiconductor bit-scaling. Over the years Lithography Engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Reducing or eliminating variability in any process will have significant impact, but the sources of variability in any lithography process are many. The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters. Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulseTM control technology. This reduction in bandwidth variation could translate in the further reduction of CD variation in device structures. The Authors will discuss the impact that these improvements in bandwidth control have on advanced lithography applications. This can translate to improved CD control and higher wafer yields. A simulation study investigates the impact of bandwidth on contrast sensitive device layers such as contacts and 1x metal layers. Furthermore, the Authors will discuss the impact on process window through pitch and the overlapping process window through pitch that has been investigated. These improvements will be further quantified by the analysis of statistical bandwidth variation and the impact on CD.

A technique for high frequency low distortion measurements

In this communication a low-cost technique for low distortion measurements at high-frequency is presented. We need to characterize the dynamic range of very low distortion linear integrated circuits over a range of 100 dB at video frequencies (around 10 MHz). Instead of buying costly distortion measuring equipment, we have preferred to build a simple and economical system for this propose.

Generation of current conveyor based sinusoidal oscillators for integrated circuits

Abstract A representative catalogue of high-frequency sinusoidal oscillators using the current conveyor as the active element is proposed. To the inherent advantages of current mode processing is added compatibility with the CMOS technology of the proposed topologies. The new structures potentially mean a drastic reduction in silicon area and an expansion in the frequency range of operation as compared with their counterparts in voltage mode.

A Low-Ripple Fast-Settling CMOS Envelope Detector

The design of a high performance envelope detector is made in this work. Proposed circuit does not need the traditional compensation between keeping and tracking required in these circuits due to a system by what the signal peaks are held in two periods and combined to obtain the envelope of the signal. Simulation results are offered comparing both the conventional and the proposed envelope detector and it is shown the superior performance of this circuit obtaining for a signal at 10MHZ smaller ripple (<1%), faster settling (0.4mus) and using smaller silicon area