P. Mortini

Dielectric reliability in deep-submicron technologies: From thin to ultrathin oxides

Abstract This paper focuses on the dielectric reliability in the thin and ultrathin oxide regime. The wear-out mechanisms and the breakdown phenomena related to the Si SiO 2 system are considered within the 12nm-5nm oxide thickness range. The degeneration evolution with respect to the oxide thickness and the consequences of the mechanisms involved in the various failure modes which limit the dielectric reliability are discussed.

On the charge build-up mechanisms in gate dielectrics

Abstract The variation of the bulk oxide charge build-up characteristics of gate dielectrics after different Fowler-Nordheim stress conditions are investigated. It is proved that none of the degradation mechanism known so far are capable of explaining the evolution of the bulk oxide degradation features after high field electrical stress. Instead, it is shown that the degradation process can be attributed to a universal charge build-up empirical law. Besides, a new and simple method for analyzing the so-called “turn-over” phenomenon in MOS structures is proposed. The method enables the monitoring of the whole Si band gap, at room temperature and without any assumption concerning the nature of the interface traps (donor-or acceptor-like). Finally, comparison between SiO 2 and nitridated oxides in N 2 O ambient is conducted in terms of volume/interface trapping properties.

Oxide reliability criterion for the evaluation of the endurance performance of electrically erasable programmable read only memories

The impact of the oxide reliability on the endurance performance of nonvolatile memories [electrically erasable read only memories (EEPROMs)] is analyzed quantitatively. The degradation rate of tunnel SiO2 layers as obtained from EEPROM cells as well as tunnel oxide capacitors subjected to different modes of electrical stress (write/erase operations, static and dynamic stress) are compared and attributed to a specific charge generation mechanism. Furthermore, a reliability criterion for the optimization of the tunnel oxide technology entering the fabrication of EEPROM cells is also proposed.

UNIFIED MODEL FOR BREAKDOWN IN THIN AND ULTRATHIN GATE OXIDES (12-5 NM)

A unified model explaining the wear-out and the breakdown of thin and ultrathin films of silicon dioxide when subjected to electrical stressing is proposed. The suggested breakdown model is based on the ability of charge trapped inside the dielectric to increase locally the effective dielectric permittivity (e) of the material by increasing the polarization locally. The impact of this local perturbation to the macroscopic characteristics of the oxide is investigated. Breakdown is correlated with the existence of a fixed amount of trapped charge inside the oxide. Moreover, the dependence of this bulk oxide trapped charge at breakdown with respect to the oxide thickness has been justified by the suggested mechanism and has been found to have excellent agreement with the experimental data.

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25‐125 8C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. DiAerent degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what eAectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 8C using inverter and pass transistor operations in a 0.35 mm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation. # 1999 Elsevier Science Ltd. All rights reserved.

Temperature, field and technological dependences of thin oxide breakdown characteristics

Abstract The influence of the temperature, the applied field, and the process on the breakdown parameters of very thin oxides used in representative CMOS technologies is studied. Particularly, three temperature ranges with different activation energies are demonstrated, although the correlation between the bulk oxide trapped charge and the breakdown vs temperature is shown. The two main well-known quantitative models for breakdown are applied and discussed. The great importance of the oxidation step is shown, but the influence of the substrate is also proved. A law describing the evolution of the field acceleration factor vs oxide thickness at high fields is given. Throughout this study, some limitations for the estimation of the oxide reliability are reported.

Aging study of optimized submicron n-MOSFET's (DC, AC and alternating stress conditions): correlation between charge pumping and classical parameters

The effects of static, dynamic and alternating stress conditions on the degradation rate of 0.8μm LDD N-channel MOS transistors have systematically been compared. The parameters used in monitoring the aging were the threshold voltage, transconductance and charge pumping current. The results suggest that, at least for our devices, the degradation induced by a.c. stress can not be explained with a quasi-static model.

Hot-carrier reliability in N-mosfets used as pass-transistors

AC-stressing is investigated to determine the hot-carrier degradations in 0.5, ¿m CMOS technology and is interpreted by a quasi-static model based on district damage mechanisms. The hot-carrier dependence of n-MOSFETs operating in Pass-Transistor configurations is carefully studied as a function of the propagation time and geometry. It is shown that the device degradation may exhibit in some cases a strong dependence with the propagation time and clearly differs from the simple case of inverter operation.

Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events

Abstract An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies.

Investigation of hot-carrier induced degradation in 0.1mm channel length n-MOSFET's

Abstract Ultra-short n-channel MOS transistors with gate lengths of 0.1μm have been analyzed in terms of hot-carrier induced degradation. The aging, performed at maximum substrate current, was monitored using the transconductance, drain current and charge pumping current. The results suggest that the degradation tends to be uniform, the degraded zone representing a large portion of the channel. Device lifetimes in excess of 10 years are predicted for nominal conditions of operation.