Nadav Mazor

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.

High-Performance E-Band Transceiver Chipset for Point-to-Point Communication in SiGe BiCMOS Technology

Two fully integrated chipsets covering the entire E-band frequency range, 71-76/81-86 GHz, have been demonstrated. These designs, which were implemented in 0.13- μm SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than -12-dBm input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71-76 GHz) and higher band (HB) (81-86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission.

A 16.2 Gbps 60 GHz SiGe transmitter for outdoor wireless links

A fully integrated 60 GHz transmitter in 130 nm BiCMOS SiGe technology for outdoor applications is presented. The transmitter covers the entire 57-66 GHz band supporting a record data rate of 16.2 Gbps at 6 dBm output power, 512 QAM with an EVM of -34 dB. The single ended saturated power, OP1dB, and OIP3 are above 18 dBm, 16 dBm and 23 dBm respectively. The transmitter meets the most stringent ETSI emission mask for point-to-point communication at class6LB, 500 MHz bandwidth with an output noise floor below -133 dBm/Hz. The area of the transmitter is 15 mm2 and it consumes 1.2 W.

A SiGe ku-band frequency doubler with 50% bandwidth and high harmonic suppression

A compact ×2 frequency multiplier covering all ku band is implemented in IBM 0.13μm SiGe technology. The transformer coupled circuit uses a common base configuration working in B- class mode and utilizes transmission lines properties to achieve harmonic suppression. The doubler covers a 3dB frequency range between 12.2 GHz to 20.4 GHz with a saturated output power above 9 dBm. The fundamental frequency is suppressed by over 27 dBc and the 4th harmonic is suppressed by more than 25 dBc across frequency band. The core design occupies only 550 μm × 620 μm and consumes 37 mW from a 2.7 V supply.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications

The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75–83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms.

A 71–86GHz multi-tanh up-conversion mixer achieving +1dBm OP1dB in 0.13 μm SiGe technology

A high output 1dB compression up-conversion mixer for the entire E band frequency range, 71-76 GHz and 81-86 GHz, is designed and fabricated in IBM 0.13 μm SiGe technology. The mixer is comprised of a double balanced Gilbert cell and a multi-tanh three transistor hybrid transconductance stage, used to enhance the mixer linearity. The conversion gain and output 1dB compression are 3.9dB and +1dBm, respectively at 71GHz and vary within 3dB and 4dB respectively over the entire 15GHz range. LO leakage is less then -30dB and noise figure is under 9dB. The circuit consumes 80mW from a 2.7V supply.

A double balanced 81–86GHz EBAND active down conversion mixer in SiGe technology

An RF to IF down-conversion mixer for the upper 81-86GHz E-BAND frequency range was designed and fabricated in IBM 0.12μm SiGe technology. The Mixer comprises of a double balanced Gilbert-cell in which the RF signal is driven through a marchand balun into the common base amplifying mixer stage. The mixer exhibits conversion gain of 7dB, SSB noise figure of 12dB and input compression I1dBCP of -10dBm. The low noise figure and high conversion gain of the mixer enables the addition of a highly linear analog controlled attenuator between the mixer and LNA to further improve the linearity of the receiver chain without degrading the noise performance. The mixer area is 0.4mm2 and it consumes 110mW from a 2.7V power supply.