Nader Shamma

Integrated approach to improving local CD uniformity in EUV patterning

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Patterning with Amorphous Carbon Thin Films

Amorphous carbon hard mask films grown with plasma enhanced chemical vapor deposition are an enabling technology for advanced front-end-of-line patterning technologies. These films must have a low etch rate and be weakly roughened in dielectric etch chemistries, high transparency at lithography alignment wavelengths, and the mechanical properties to mitigate elastic instabilities such as line bending. The deposition process affects all of these parameters through the resulting structure and composition. Highly graphitic films deposited at 550°C are common; however, other process spaces relying on ion bombardment rather than temperature can create less graphitic films with improved film properties like transparency, hardness, and etch selectivity.

Unbiased roughness measurements: the key to better etch performance

Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and known to increase with the introduction of EUV lithography. However, despite recommendations from ITRS, NIST, and SEMI standards, the industry has not agreed upon a methodology to quantify these properties. Thus, differing methodologies applied to the same image often result in different roughness measurements and conclusions. To standardize LWR and LER measurements, Fractilia has developed an unbiased measurement that uses a raw unfiltered line scan to subtract out image noise and distortions. By using Fractilia’s inverse linescan model (FILM) to guide development, we will highlight the key influences of roughness metrology on plasma-based resist smoothing processes. Test wafers were deposited to represent a 5 nm node EUV logic stack. The patterning stack consists of a core Si target layer with spin-on carbon (SOC) as the hardmask and spin-on glass (SOG) as the cap. Next, these wafers were exposed through an ASML NXE 3350B EUV scanner with an advanced chemically amplified resist (CAR). Afterwards, these wafers were etched through a variety of plasma-based resist smoothing techniques using a Lam Kiyo conductor etch system. Dense line and space patterns on the etched samples were imaged through advanced Hitachi CDSEMs and the LER and LWR were measured through both Fractilia and an industry standard roughness measurement software. By employing Fractilia to guide plasma-based etch development, we demonstrate that Fractilia produces accurate roughness measurements on resist in contrast to an industry standard measurement software. These results highlight the importance of subtracting out SEM image noise to obtain quicker developmental cycle times and lower target layer roughness.

Ultimate edge-placement control using combined etch and lithography patterning optimizations

Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho cooptimization to less than 1.0nm 3σ. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

PDL oxide enabled pitch doubling

A double patterning (DP) process is introduced with application for advanced technology nodes. This DP technique is enabled by a novel low-temperature pulsed deposition layer (PDLTM) oxide film which is deposited directly on patterned photoresist. In this article, we will report the results of fabrication of sub-50nm features on a 100nm pitch by the PDL-spacer DP process using 0.85 NA dry ArF lithography. This result represents the potential of the PDL-based DP to significantly enhance the resolution of the patterning process beyond the limits of optical lithography. Components of CD variance for this spacer DP scheme will be discussed.