Nadia Rezzak

The sensitivity of radiation-induced leakage to STI topology and sidewall doping

Abstract The sensitivity of radiation-induced source–drain leakage to the amount of recess in the shallow-trench isolation (STI) of CMOS technologies is reported. The impact of the doping profile along the STI sidewall on the magnitude of the leakage current is quantified. The sensitivity of the radiation-induced leakage current to these parameters provides insight into how process variability is manifested as variations in the radiation response.

Layout-Related Stress Effects on Radiation-Induced Leakage Current

The effects of shallow-trench-isolation-induced mechanical stress on radiation-induced off-state leakage current are reported in 90-nm NMOS devices. The radiation-induced leakage current increases with increasing active device-to-isolation spacing. The leakage current also depends on channel width; narrow devices exhibit less leakage before irradiation, but more after irradiation. These geometrical factors affect the mechanical stress in the device, which impact the dopant diffusion and activation and the charge trapping in the STI oxide. The combined effects of these layout-related phenomena affect the sensitivity to radiation-induced charge.

Including the Effects of Process-Related Variability on Radiation Response in Advanced Foundry Process Design Kits

Space applications using advanced foundry processes require device models that accurately include the dependence of total-ionizing dose (TID) response on process variability and layout. An automated flow is described for TID-aware process design kit generation using new test chips, modeling, and simulation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.

High fluence 1.8 MeV proton irradiation effects on n-type MOS capacitors

MOS capacitors with 7 nm SiO2 dielectrics and n-doped Si substrate were irradiated by 1.8 MeV protons with fluences ranging from 1012 to 5 × 1013 cm−2 which correspond to the typical LHC fluence range. No significant increase in gate oxide leakage current was detected. A decrease of the capacitance was observed in the accumulation regime. This effect is explained by an increase of the substrate resistivity caused by displacement damage.

Including Radiation Effects and Dependencies on Process-Related Variability in Advanced Foundry SPICE Models Using a New Physical Model and Parameter Extraction Approach

An automated flow is described for total-ionizing dose (TID)-aware SPICE model generation that includes TID response and its dependence on process variability and layout. A memetic algorithm that balances multiple objectives, subject to realistic constraints, is introduced for global optimization of the flow. A differential evolution algorithm is adapted for global exploration, and a modified random pattern search strategy is introduced for local exploitation. The optimizer efficiently reduces the value of different kinds of objective functions in the extraction at reasonable cost and avoids premature convergence in most practical cases. The model is implemented in Verilog-A, can be applied to all foundry model formats, and supports all popular SPICE simulators. To validate the flow, simulations from models extracted from specific targets are compared with measured current-voltage characteristics under various irradiation conditions for 0.35 μm, 0.18 μm, and 90 nm bulk CMOS processes.

Total-ionizing-dose radiation response of partially-depleted SOI devices

The high body doping inherent in sub-100 nm partially-depleted SOI devices tends to mitigate the sensitivity to TID-induced leakage, providing that the doping reaches the STI sidewalls and back channel. Measured TID response on 45 nm NMOS SOI is consistent with trends observed in simulations.

Total-ionizing-dose radiation response of 32 nm partially and 45 nm fully-depleted SOI devices

TID-induced changes in 32 nm PD SOI devices depend on the device variant: low VT devices show minor increased in leakage, high VT devices show negligible change. Simulated sensitivity of TID to the gate work function of the high-k metal gate and associated doping changes confirm that the body doping remains high and generally mitigates TID sensitivity. Preliminary ring oscillator measurements show no measurable change in supply current or frequency with TID. Specially designed experimental 45 nm SOI FDSOI devices exhibit a pronounced TID-induced VT shift due to the coupling with the BOX layer.

A Novel 65 nm Radiation Tolerant Flash Configuration Cell Used in RTG4 Field Programmable Gate Array

The newly introduced radiation-tolerant flash-based FPGA, RTG4, uses a novel configuration cell design composed of a NMOS switch controlled by a totem pole p-channel flash and n-channel flash construction. Its radiation tolerance is far superior to that in the present available Flash-based FPGA. This paper describes the radiation hardening by design (RHBD) process for the new flash-based configuration cell. A subtle and unique retention issue was found and resolved through studying physical mechanisms and conducting experiments.

Single Event Latch-Up Hardening Using TCAD Simulations in 130 nm and 65 nm Embedded SRAM in Flash-Based FPGAs

In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number of SRAM cells included in the 3D structure significantly affects the SEL threshold. The number of SRAM cells needs to be optimized for accurate SEL prediction within a reasonable simulation time.The simulation results are validated using heavy ion and neutron data. After trade-off studies, process mitigation solutions are chosen to improve the SEL threshold in 65 nm and achieve immunity in neutron environment.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.