Ebin Liao

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Development of 3-D Silicon Module With TSV for System in Packaging

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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One of challenge for the 3D integration by the TSV approach is the electroplating. Electroplating quality and time are important parameters for TSV cost and application. Solid Cu filling TSV (Through Si Via) with via diameter 20 μm and 65μm depth is achieved by the DC (directly current) electroplating within 40 minutes on 8 inch wafer.

FCBGA Package With Through Silicon via (TSV) Interposer

The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling.

Fast electroplating TSV process development for the via-last approach

In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage monitor. Wafer warpage reduction is achieved by process stage modification.

3D interconnection process development and integration with low stress TSV

We report the process evaluation and integration for the embedded RF passive device in this paper. Two sets of test vehicle were designed and fabricated for the evaluation of RF passive devices embedded in USG (undoped silicate glass) and BCB (Benzocylcobutene) dielectric. We encountered resistor uniformity issue and BCB capacitor limitation during the process set up. After process issue solving and final platform setting, resistor, capacitor, inductor and bandpass filter were integrated and the high performance functions were demonstrated.

Characterization and management of wafer stress for various pattern densities in 3D integration technology

A passive MEMS magnetostatic relay using only one electroplated magnetic layer was presented. The relay consists of an electroplated Ni80Fe20 plate supported by a pair of torsion bars from two sides. The relay is actuated by approaching an external magnet to the relay. The switching-on magnetic field is about 4.8 mT and the contact resistance is about 3 Ohms with gold contact. The lifetime testing shows more than 7.5 million hot switching cycles with 1–2 mA current. This passive magnetic relay could find applications in portable electronics, such as cellular phones, personal data assistant (PDA), pace makers, hearing aids, etc.

High performance embedded RF passive device process integration

A passive magnetostatic microelectromechanical systems (MEMS) switch using only one electroplated soft magnetic layer of nickel-iron (Ni80Fe20) alloy was designed, fabricated, and characterized. The switch is composed of an electroplated Ni80Fe20 plate supported by a pair of torsion bars from two sides. The Ni80Fe20 plate is patterned into long and narrow strips to improve the sensitivity. The switch is actuated by bringing an external magnet closer to the switch. Therefore, no internal electrical power is consumed by the device for actuation. The magnetic field required to turn on the switch is 4.8 mT, and the initial contact resistance is 0.5 Ω with gold contacts. The switch has been tested to pass more than 34 million hot-switching cycles at 2-mA current at room temperature when packaged at the wafer level with SU-8 sealing. The die size is 2.1 × 1.94 × 1.1 mm3. The magnetic switch of this paper has the potential to replace the conventional reed switch in portable electronics such as laptops, cellular phones, personal data assistants, pacemakers, and hearing aids.

Micromachined passive magnetostatic relays for portable applications

An IMC based low temperature solder <200 °C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.