Nam Sung Kim

Successful fault isolation of bit line leakage and leakage suppression by ILD optimization in embedded flash memory

This paper discussed specifically by focusing on failure analysis study for the successful fault isolation of bit line to bit line (BL) leakage and the formation mechanism of electrical conducting path inside inter level dielectric (ILD) oxide between bit lines in flash cell arrays that has extra topography resulting from two stacked poly-Si layers, which causes the abnormal leakage current during the initial cycling test (a few times of erasing and programming) for flash memory device using high voltage application. In addition, we demonstrate the suppression of this leakage current by optimizing ILD deposition process, resulting in the significant yield improvement as well as better process margin across a wafer.

Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory

We have intensively investigated the impact of Titanium (Ti) deposition condition along with optimal Ti thickness and subsequent rapid thermal annealing (RTA) process on each contact resistivity (Rc) characteristics of W-bit line in sub-micron dynamic random access memory (DRAM) technology. We found out that low pressure (LP) Ti deposition method with a subsequent RTA temperature above critical value is very efficient to improve the uniformity of Ti deposited thickness inside the contact hole as well as to remove the agglomeration in the contact area of periphery n+ and p+ active regions, resulting in the dramatic Rc reduction with a good uniformity across a wafer. In addition, the optimized condition of Ti deposition and RTA process suitable to 0.15 µm DRAM and beyond is proposed to reduce W-bit line Rc of cell and periphery areas simultaneously, while still keeping the good electrical properties for other significant parameters such as junction leakage and data retention time.

Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells

We have investigated the impact of gate etch post-cleaning process on the tail distribution of data retention time in dynamic random access memory (DRAM) cells having polymetal (W/WNx/Poly-Si) gate device based on the fully mature technology of sub-micron DRAM. In this paper, we propose the optimized gate etch post-cleaning condition in polymetal gate device to guarantee the characteristics of DRAM data retention time comparable to that of the conventional polycide (WSix/Poly-Si) gate etch post-cleaning process. In addition, for the first time, we have verified that the effective removal of the unwanted residue generated by gate etch improves the interface quality of the remaining oxide at the gate edge, resulting in improving the tail component of data retention time.

Low-Damage Gate Etching with High Degree of Anisotropy in High-Density DRAM Cell

We have investigated low-damage gate etching with a high degree of anisotropy in a high-density dynamic random access memory (DRAM) cell. In this paper, we propose the bias combination mode as an effective gate etch scheme, in which time modulation (TM) bias is applied to the high-Vpp (peak-to-peak value of bias voltage) main etching and continuous wave(CW) bias is applied to low-Vpp overetching. In addition, we report, for the first time, that the gate etching method employing the bias combination mode enables us to improve the degree of anisotropy significantly, while still keeping a good tail component of the retention time for 0.18 µm DRAM and beyond.

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond J.-P. Han, T. Shimizu, L.-H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, A. Azuma, G. Yang, M. Eller, D. Jaeger, H. Zhuang, K. Miyashita, K. Stein, D. Nair, J.-H. Park, M. Hamaguchi, S. Kohler, D. Chanemougame, W. Li, K Kim, N. Kim, C. Wiedholz, S. Miyake, G. Tsutsui, H. van Meer, J. Liang, M. Ostermayr, J. Lian, M. Celik, R. Donaton, K. Barla, M.H. Na, Y. Goto, M. Sherony, F. Johnson, R. Wachnik, J. Sudijono,E. Kaste, R. Sampson, J.-H. Ku, A. Steegen, W. Neumueller Infineon Technologies, Renesas, IBM Microelectronics, STMicroelectronics, Toshiba America, GLOBALFOUNDRIES, Samsung Electronics, alliances at IBM SRDC, 2070 Rt 52, Hopewell Junction, NY12533; jh262@ieee.org,

Investigation on Metal Pillar Defect in sub-micron CMOS Technology

We have investigated the metal pillar defect induced by tungsten (W)-plug missing inside contact hole sitting on the long W-plug LIL trench line in sub-micron CMOS technology. It is found that W-plug LIL trench line may have a seam due to high aspect ratio, resulting in W contact-plug missing caused by out-gassing from a seam inside the long trench LIL line. This missing W contact-plug can make defect like pillar shape after metal etch. The key process parameters for W contact-plug missing to cause metal pillar defect have been discussed. We reported the importance of process optimization on W-gap filling at LIL stage to avoid both W contact- plug missing and the metal pillar defect by proposing the methods to obtain better process margin.

Impact on Off-state Leakage Current in PMOS Device by Metallic Contamination

The impact of metallic contaminations on off-state leakage current in pMOS device is intensively studied in sub-micron CMOS technology. It is found that anomalous high loff leakage ofpMOS device (nMOS not affected) shows the strong correlations to high frequent use of control wafer in a wet bench for pre-cleaning process prior to spacer oxide deposition as well as long queue (Q)-time between after pre-cleaning and before spacer oxide deposition. I-V analysis has proved that this off leakage of pMOS is mainly due to p-n (drain-well) junction leakage in reverse bias mode. Further examination for both nMOS and pMOS loff leakage behaviors seems to show metallic contamination which can efficiently act as recombination centers with deep level by pairing metallic impurity-boron in the p-type doped silicon, resulting in affecting the reverse bias p-n junction leakage ofpMOS transistor only. A new approach to reduce this loff leakage by introducing rapid thermal annealing (RTA) before pre-cleaning process is recommended to prevent metallic impurity from diffusing through the screen oxide layer.

Impact of untreated thicker CVD TiN film at a Via glue layer on Rc Performance in 0.15um CMOS Technology

In this work, it is reported that the mechanism was studied on abnormal via contact resistance (Rc) and the promising solutions to improve via Rc were proposed. We found out that via Rc is very sensitive to CVDTiN plasma treatment efficiency and also a slight fluctuation of CVDTiN thickness could significantly increase the amount of untreated CVDTiN film, leading to higher via Rc. This paper focuses on the impact of untreated thicker CVDTiN film at a via glue layer and the improvement solution of via Rc

Control gate-bit line leakage induced cobalt silicide migration in 0.15/spl mu/m embedded flash memory devices

It has been discovered that electrical stress causes both the decomposition of CoSi2 and the diffusion of Co atoms into control gate polycrystalline Si in our 0.15mum embedded flash memory devices. After simulation with the N+ poly and P+ poly resistors to further understand the abnormal phenomenon, we found two things: mainly, that the current breakdown depends on the biased voltage and that the P+ poly resistor suffers the current breakdown earlier than the N+ poly resistor. This, in turn, we found to be due to a higher self-heating effect in the bulk Si underneath CoSi2 in the P+ poly resistor than N+ poly resistor. We believe there is a certain level of current density required to trigger this abnormal CoSi2 decomposition; when the current density exceeds that critical density point, it causes the CoSi2 to decompose into Co and Si and also migrate Co atoms. This, in turn, reduces the thermodynamic free energy of the system. From the I-V characteristic, it is also observed that this self-heating effect contributes to the decomposition of CoSi 2. Additionally, the conclusion has been made that the critical current density depends on the area of current path of the thin CoSi2 layer on the top of the bulk silicon. Furthermore, the direction of the current flow was also concluded to determine the direction of Co atom migration

A new low temperature APM cleaning process to improve ONO integrity in 0.18μm stacked-gate EEPROM memory

Introduction Inter-poly dielectric thickness dominates program/erase speed and the amount of read current for a nonvolatile memory cell transistor with a stacked-gate structure. OxideNitride-Oxide (ONO) stacked film has been widely used as an inter-poly dielectric in stacked-gate flash EEPROM devices for the improvement of the reliability problem due to the degradation of data retention capability occurring during the long-term memory operation [1,2]. ONO has been reported to show high breakdown voltage and low defect density. There are many factors, which affect the quality and uniformity of ONO film during the process. In the present study, low temperature APM (LT-APM) clean (<50oC) is the 1 time introduced as the cleaning process after ONO deposition to improve the integrity of ONO film. The typical clean after ONO deposition before high voltage gate oxide growth is the normal APM (N-APM) also commonly known as SC1 clean, it is a mixture of NH4OH/H2O2/H2O at temperatures between 70 and 90oC. The purpose of the APM clean is to remove organic particles. It was reported in the literature that SC1 process has an impact on surface roughening , yield loss due to the degradation of dielectric breakdown , etching of silicon , and oxide loss . In our study, it has been found out that better ONO integrity with less surface roughness, better uniformity, hence, longer Time Dependent Dielectric Breakdown (TDDB) and stable ONO thickness have been achieved by using this LT-APM clean. Further study found out that the temperature of the APM play a dominant role in the roughness improvement, instead of the concentration of the chemical. Experimental All the devices studied in this work were fabricated using 0.18μm CMOS EEPROM technology. The ONO stack separates the floating gate and the control gate. It consists of a layer of SiO2 at the bottom, a Si3N4 layer in the centre and another SiO2-layer on top. The SiO2 is deposited as High Temperature Oxide (HTO) at 780oC. The basic process related with ONO deposition is shown in Fig 1. A Flash cell starts with tunnel oxide at the bottom, followed by the floating gate poly and ONO deposition. Subsequently, poly etch is done to grow high voltage gate oxide. A clean step is introduced before control gate poly deposition to clean the top oxide of ONO. Comparison between LT-APM and NAPM and their effects on ONO were studied. The composition, temperature and process time of N-APM and LT-APM used in this study are summarized in Table 1.