Namhoon Kim

Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV)

New concept of interposer in FPGA system will be introduced. The interposer includes a lot of TSVs for the high speed signals. Technology requirements and manufacturing process to support multi-gigabit or tens-of-gigabit per second SerDes application will be presented. The interposer needs to be accurately modeled over the high frequency by considering all those requirements before design optimization. An interposer test vehicle was fabricated for measurement and verification. The measurement technique using vector network analyzer including de-embedding process will be introduced. At the same time, TSV high frequency modeling methodology will be disclosed. Both broadband s-parameter model and RLC lumped model based on physical structures were generated. The interposer could be a passive component or an active component with circuit. The passive interposer has an advantage in a certain area and the active interposer also has its own. The depletion area in silicon substrate will be considered as well to increase the level of accuracy. The routing metal loss in under bump metallurgy (UBM) layer should be analyzed also. Finally, full channel analysis has been done. It includes optimized interposer model on top of package substrate and printed circuit board. Each proposed interposer structure enables high performance signaling and great visibility in both passive and active interposer.

Advancing high performance heterogeneous integration through die stacking

This paper describes the industrys first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. Optimization took place concurrently on multiple facets of the design which were necessary to successfully implement the 3-D integration. In particular, this paper outlines the choices that were made in terms of package substrate material and interposer resistivity in order to optimize 28Gb/s system channel characteristics. These choices were validated through extensive electrical simulation and test chip correlation. In addition, this paper describes the design and timing verification of inter-die interconnects, an area that the electronic design automation industry had not yet fully addressed. This paper further describes 3D thermal-mechanical modeling and analysis for package reliability. The modeling was performed to address package coplanarity issues and stresses imposed by the interposer on the active dice, the low-k dielectric material, the micro-bumps and the C4 attach. The results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

Spiral via structure in a BGA package to mitigate discontinuities in multi-gigabit SERDES system

Multi-gigabit serial channel design has become more and more important since channel margins are becoming tighter as operating frequencies increase. Most engineers working on these channels have been plagued by several different types of signal integrity problems including impedance discontinuities, reflections, attenuation, undershoot and overshoot, and crosstalk. In reality, many signal integrity problems are caused by impedance discontinuities. These discontinuities can be caused by physical discontinuities, system parasitics, or design mistakes. We need to understand these discontinuity issues to improve full channel from package to PCB board. When most designers simulate a channel, they concatenate separate package and PCB models. Using these concatenated models they simulate the data path in a channel simulation test bench. This piecewise or concatenated channel model is incomplete because it does not carefully consider the interface between the BGA package and the PCB. The hidden factor which makes the concatenated channel model differ from real channel measurement will be disclosed in this paper. A more detailed solder ball analysis has also been done during this process. We learn from the above results that if the package is soldered down to the PCB and measured together, additional loss occurs due to the package to board transition. The combined channel is more capacitive than the concatenated channel in the package to board transition region. The excess capacitance due to BGA solder ball transition is due to the physics of the interface and can not be easily eliminated. It is shown that system performance degradation is very sensitive to the impedance discontinuity introduced at the BGA/PCB interface. This paper will introduce a spiral via structure which is shown to be a more effective way to compensate the transition discontinuity seen at the BGA/PCB interface. This paper also shows how the spiral via structure was implemented and optimized in the BGA package. The overall channel performance improvement by using spiral via structures in BGA package is proven by the simulation and measurement.

Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology

Bandwidth demand is exploding due to internet video/TV streaming, Web surfing, file sharing, VoIP, video calling, online gaming, and etc. The bandwidth requirement leads us to develop 400G line card solution for communication systems. 28Gb/s electrical interface can increase port density and reduce power per bit. New heterogeneous SSIT (Stacked Silcon Interconnect Technology) design to implement 28Gb/s SerDes transceivers into an FPGA package will be introduced. The silicon interposer was used in this technology and it includes a significant number of TSVs (Through Silicon Vias) for the high speed signals. It is imperative that the signal path including the interposer is accurately modeled over the high operating frequency range by considering all those requirements before design optimization. Detailed design optimization for interposer has been performed to evaluate optimum design rules by taking into consideration of manufacturability and the TSVs parasitic effects from DC to high frequency, which can cause major performance degradation. A package channel design methodology for 28Gb/s SerDes signal support will be introduced. The package material selection to minimize dielectric loss and trace design to minimize copper/surface roughness loss for package substrate are very important. In addition, the design topologies to minimize signal attenuation loss, reflection loss, crosstalk and power coupling noise will be presented. Package and PCB design co-optimization is very important to minimize reflections from solder ball interface. Any single mismatch in the very high speed system can result in the significant closer of the eye diagram. Once full channel analysis has been performed including optimized stacked silicon interposer model on top of low loss package substrate and PCB model, the simulation data is compared to the measured 28Gb/s Eye diagram and showing very good correlation. The proposed optimized channel system enables high performance signaling and great visibility of 28Gb/s Serdes FPGA applications.

Performance analysis and optimization for silicon interposer with Through Silicon Via (TSV)

In this paper, the stacked silicon interconnect technology in FPGA system is introduced, which needs to be accurately modelled over high frequency by considering numerous design requirements. The stacked silicon interposer includes a lot of TSVs for high speed signals. Designs without the consideration of high frequency effects of TSV will degrade the rise/fall time of a signal, increase crosstalk and noise injection, and cause significant performance degradation on high speed channels. The routing metal loss in Under Bump Metallurgy (UBM) layer is also analyzed and simulated. Performance enhancement by using SOI wafer is shown and compared against conventional wafers.

Understanding loss mechanisms of passive interconnects with innovative/cost effective structure implementations for supporting 28Gbps and beyond transmission

Channel loss budgets are becoming more stringent as operating speeds increase. The loss mechanisms of these high-speed channels need to be properly understood in order to minimize the channel loss. The conductor loss, including skin effect loss and surface roughness loss as well as dielectric loss will be addressed theoretically and practically in various cases. This paper will study and identify which losses are primarily responsible for determining system performance in various cases.