Joong-Ho Kim

Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems

Accurate modeling of transmission lines becomes increasingly important in high-speed interconnect system design. However, it is rather difficult to obtain broadband transmission line models, in particular using frequency-domain measurements. This paper points out two potential accuracy issues. First, inaccurate DC values of the frequency-domain data cause a severe error in the time-domain simulations. Second, it is difficult to characterize the characteristic impedance over a wide frequency range due to the reflection caused by the port discontinuities. This paper proposes the combination of both time and frequency measurement data to mitigate the DC accuracy issue. For the characteristic impedance model, a new de-embedding technique is presented to mitigate the port discontinuity issue. Several numerical examples, such as MCM-L coplanar lines and package microstrip lines, are studied to validate the accuracy of the proposed method.

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Modeling and analysis of power distribution networks for gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes increasingly important to accurately characterize and analyze power distribution networks (PDN). This paper presents the modeling, simulation, and measurement of a PDN in a high-speed FR4 printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps and above. The test board consists of two transceiver chips placed on wire bond plastic ball grid array (PBGA) packages. The applied analysis method is a hybrid technique that combines the interactions of the power planes, interconnects, and the nonlinear drivers. The power planes and interconnects are modeled using the transmission matrix method (TMM) and rational interpolation, respectively. Then macro modeling is applied to generate reduced-order models to efficiently analyze the whole system including the nonlinear drivers using conventional circuit simulation tools such as SPICE. The transfer characteristics of the power planes are calculated and the effects of the decoupling capacitors and power supply noise are studied. The simulation results are also correlated with measurement data to verify the validity of the method.

Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

Challenges and solutions for next generation main memory systems

Todays high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view.

S-parameters Based Transmission Line Modeling with Accurate Low-Frequency Response

Accurate transmission line modeling is required for multi-gigahertz designs. To capture high frequency effects such as frequency-dependent dielectric and conductor loss, S-parameters obtained from VNA measurement are commonly used to model transmission lines. Unfortunately, such method has not been very robust since the S-parameters from VNA measurement have a low frequency limit. In this paper, we present a method to obtain a broadband transmission line model with accurate low-frequency response. A conversion formale from the S-parameters to RLGC models is first derived for multi-conductor transmission lines. We then demonstrate the inaccuracy in transient waveforms of transmission line models due to inaccurate low frequency response. Finally we present a method to calculate the accurate low-frequency response using TDR time-domain measurements in addition to VNA frequency domain measurements

Pseudo-differential signaling scheme based on 4b/6b multiwire code

The majority of todaypsilas memory interfaces use single-ended signaling instead of differential signaling. Extending the performance of single-ended systems beyond a few Gb/s is a very challenging task mainly due to crosstalk and SSO noise. This paper presents a pseudo-differential signaling scheme based on an encoding technique which maps 4 bits of data to six coded bits with balanced numbers of 0s and 1s. The proposed scheme successfully removes the impact of SSO and VREF noise. The simulation results based on graphics memory channels show significant improvements in performance over the non-coded case.

Power delivery design for 800MHz DDR2 memory systems in low-cost wire-bond packages

This paper describes the challenges in designing supply networks of high-speed interface systems in low-cost wire-bond packages. It introduces a set of figure-of-merits for the supply noise performance of interface systems. It then demonstrates how these parameters can be used to guide the design and verification of interface power distribution networks

Power integrity characterization and correlation of 3D package systems using on-chip measurements

System power integrity characterization for low-power high-speed memory interface in a 3D package system is a challenging task due to probing difficulties imposed by small form factor. In this paper, power integrity measurements including supply noise, PSIJ sensitivity and PDN impedance curve using on-chip noise generator and monitors are presented. On-chip measurement data are validated by off-chip sense line measurements. Good correlations between simulation and measurements close the loop between analysis and verification for the system power supply delivery design.

A study of reduced-terminal models for system-level SSO noise analysis

SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.