Naohiko Kimizuka

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.

Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

This paper reports 65-nm node ultra-low standby power CMOS technology for mobile applications, utilizing the combination of HfSiON FET and back-biasing scheme for the first time. With well-optimized channel, offset-spacer and halo conditions, physical gate length is successfully scaled down to 55 nm with excellent V/sub th/ roll-off and small DIBL, for both surface channel nFET and buried channel pFET. The record I/sub on//I/sub off/ ratio, the drive current of 510/220 /spl mu/A//spl mu/m with off-state leakage of 20/20 pA//spl mu/m, are obtained. We have also demonstrated body-biasing scheme feasibility for further subthreshold leakage (I/sub subth/) reduction. By exploiting Fermi-level-pinning effect, we have reduced the channel doping concentration and suppressed gate induced drain leakage (I/sub GIDL/) even under reverse body-biasing condition. Total standby leakage (I/sub subth/+I/sub GIDL/+I/sub g/) are reduced to 1.4/0.32 pA//spl mu/m at V/sub dd/= 0.8 V and Vb= /spl plusmn/1 V, which is the smallest value ever reported for 65nm-node LSTP.

A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliability

We have newly developed poly-Si/a-Si/HfSiON (EOT=1.6nm) transistor that features high I/sub on/-I/sub standby/ ratio and reliability for 65nm-node LSTP (Low Standby Power) application. By carefully optimizing halo implant condition, excellent I/sub on/-I/sub standby/ (=I/sub g/I/sub off/) characteristics of I/sub on/=520/spl mu/A/I/sub standby/=17pA (I/sub g/=1.6pA, I/sub off/= 15pA) at V/sub dd/=1.2V are obtained, which is the highest ratio ever reported. In addition, we have newly introduced thin amorphous-Si layer between HfSiON and phosphorous-doped poly-Si gate-electrode for reliability enhancement, and confirmed that PBTI (positive bias temperature instability) lifetime improves by two orders of magnitude with no performance degradation. We believe this technology enables further device scaling of poly-Si/HfSiON structure.

A new degradation scheme for direct-tunneling ultrathin gate dielectric

Summary form only given. A new degradation scheme for ultrathin gate dielectric is presented on the basis of gate current. By using Drain Avalanche Hot Carrier (DAHC) injection, we demonstrate for the first time that the hot-carrier induced trapping enhances the direct-tunneling gate leakage current of MOSFETs. We also show that oxynitrided dielectric exhibits a higher resistance against hot-carrier injection. Moreover, an anomalous increase was found without affecting Gm degradation trends under hot-carrier stressing. Therefore, gate current is a very important parameter in the reliability of ultrathin gate dielectric.

A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

We have developed a novel technology for formation of source/drain regions in 0.13 /spl mu/m MOSFETs. A combination of low-energy arsenic (8 keV) implantation and assist-phosphorous implantation suppresses transient enchanted diffusion (TED) of boron, and this improves I/sub on/-I/sub off/ characteristics as well as V/sub th/ roll-off. Assisted by low-dose phosphorous implantation, this technology can minimize both junction-leakage current and gate-poly depletion. An I/sub dsat/ of an nMOSFET of 750 /spl mu/A//spl mu/m (with t/sub ox//sup inv/ of 3.3 nm at 1.5 V) was obtained.

Reliability scaling in deep submicron MOSFETs

This paper reviews scaled reliability of deep sub-micron MOSFETs, including hot-carrier effects and oxide-breakdown. On the point of practical device design, the former constrains the maximum applicable voltage with the scaling factor of k-1/2. The latter give that with the scaling fact of k-1. It is shown that the limiting factor of operating voltage switches from hot-carrier effects to thin oxide reliability at a 0.25 micrometers device.