Naoki Miyamoto

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-/spl mu/A low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V/sub vv/ of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm/sup 2/ 128-Mb experimental chip was fabricated using 0.25-/spl mu/m technology.

Internal voltage generator for low voltage, quarter-micrometer flash memories

A fabricated bandgap generator using 0.25-/spl mu/m Flash memory process generated a stable reference voltage under 4 V, boosted from an external power supply of 2.5 V. The generated voltage was 1.297/spl plusmn/0.025 V at a power supply of 4 V/spl plusmn/10%; the temperature dependence was +0.7 mV//spl deg/C. The characteristics of a triple-well bipolar transistor for the Flash memory process are sufficient for a reference voltage generator; f/sub T/ is 230 MHz, and H/sub FE/ is 70. Dynamic operation reduced the average current consumption from 306 to 8.6 /spl mu/A. Fabricated voltage-doubler circuits generated a voltage 1.8 times larger than that from conventional charge-pump circuits.

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme.<<ETX>>

Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories

A 105.9 mm/sup 2/ 128 Mb experimental chip using 0.25 /spl mu/m technology demonstrates the feasibility of circuits that take advantage of the potential scalability of flash memory cells and an accurate internal voltage generator that operates at 2.5 V Vcc: (1) a layout-pitch-relaxing bit-line clamped sensing multiplex and intermittent-burst data transfer (four phases with 500 ns/20 ns) for a 3F (F=feature size) pitch, and (2) a 5 /spl mu/A dynamic band-gap generator under a boosted voltage using triple-well bipolar transistors and a voltage doubler charge pump, for accurate 10 to 20 V generation.

High reliability electron-ejection method for high density flash memories

To minimize the electrical stress for electron-ejection of each flash memory cell, the variable word-line voltage (VVP) method and the variable pulse width (VVWP) method are proposed. Both methods make it possible to achieve high reliability while maintaining the total operating time of the conventional method, and both provide a sufficient disturb margin. Simulation results show that both methods reduce the maximum Fowler-Nordheim tunnel current density by 1.4 orders of magnitude compared to that of the conventional method, and the VVWP method increases the number of verifications by much less than the VVP method. This is expected to triple the charge-to-breakdown (Q/sub bd/) by decreasing the trap generation. A Q/sub bd/ higher than the injection charge as obtained, as needed for high density flash memories.

20-Mb/s erase/record flash memory by asymmetrical operation

The high density and low power of a flash memory makes it attractive for use as a temporary file memory of moving-pictures in future personal HDTV movie cameras with MPEG2 encoders. In this application, the recorded images are likely to be down-loaded to a permanent file within a month, and the total number of times each memory card is used will probably be less than 10/sup 4/. However, the target recording rate of 20 Mb/s is one order faster than that of the conventional flash memory. This paper, therefore, proposes high-speed erase/record circuit technologies based on asymmetrical operation, in which Vthi is set below the threshold voltage of the recording state. This scheme with accurate fast bit control, continuous record operation, and multi-phase word driving, makes 20 Mb/s erase/record flash memories attainable.

Highly Reliable N2O-Oxynitrided Tunnel Oxides for Flash Memory

Cycling of up to lff is conhrmed in a flash memory cell with Np-oxynitrided SiQ as a tunnel oxide. This improvement is shown to be realized by annealing a SiO2 film in Np ambient in a conventional furnace. XANES (X-ray AbsorptionNearEdgeStructurQ analysis clarifies thatthe higher resistance of an oxynitrided SiO, film to high electric-field stress is due to *re presence of fewer unstable Si O bonds than in conventional SiO, film.