Naoto Miyashita

Properties of high-performance porous SiOC low-k film fabricated using electron-beam curing

In this paper, we describe the effect of electron-beam (EB) curing on ultra-low-k dielectric porous SiOC material (k=2.2) and the application of this technology to the 90-nm-node Cu/low-k multilevel damascene process. A significant improvement of dielectric porous SiOC films with EB curing has been demonstrated. The mechanical and adhesion strength of these films were increased by a factor of 1.5–1.6 without degrading the films k. This result can be explained by the reconstruction of a Si–O random network structure from cage Si–O bonds and Si–CH3 bonds through EB curing. Additionally, the EB curing of spin-on dielectric (SOD) porous low-k films contributes to a decrease in their curing temperature and a decrease in their curing time. Under optimum EB curing conditions, no degradation of transistor performance was revealed. The excellent adhesion strength obtained by EB curing, has contributed to the success of multilevel damascene integration. On the basis of our findings, this EB curing technology can be applied in devices of 65-nm-node and higher.

Notable improvement in porous low-k film properties using electron-beam cure method

High performance Low-k dielectric with porous structure (k=2.2) is realized by Electron-Beam (EB) cure technique, and applied to a 90 nm node Cu/Low-k multilevel damascene process. By EB curing, while maintaining a low k value, both mechanical strength and adhesion strength of lower interface have been improved 1.5 times respectively. This strengthening effect was actually confirmed as avoiding peeling by CMP process. In addition, introduction of EB cure technique reduced spin on dielectric (SOD) cure temperature and time, therefore the thermal budget was reduced drastically. It was also considered that this EB cure technology will be very effective in future 65 nm node devices.

Visualization and automatic detection of defect distribution in GaN atomic structure from sampling Moiré phase

Quantitative detection of defects in atomic structures is of great significance to evaluating product quality and exploring quality improvement process. In this study, a Fourier transform filtered sampling Moiré technique was proposed to visualize and detect defects in atomic arrays in a large field of view. Defect distributions, defect numbers and defect densities could be visually and quantitatively determined from a single atomic structure image at low cost. The effectiveness of the proposed technique was verified from numerical simulations. As an application, the dislocation distributions in a GaN/AlGaN atomic structure in two directions were magnified and displayed in Moiré phase maps, and defect locations and densities were detected automatically. The proposed technique is able to provide valuable references to material scientists and engineers by checking the effect of various treatments for defect reduction.Quantitative detection of defects in atomic structures is of great significance to evaluating product quality and exploring quality improvement process. In this study, a Fourier transform filtered sampling Moire technique was proposed to visualize and detect defects in atomic arrays in a large field of view. Defect distributions, defect numbers and defect densities could be visually and quantitatively determined from a single atomic structure image at low cost. The effectiveness of the proposed technique was verified from numerical simulations. As an application, the dislocation distributions in a GaN/AlGaN atomic structure in two directions were magnified and displayed in Moire phase maps, and defect locations and densities were detected automatically. The proposed technique is able to provide valuable references to material scientists and engineers by checking the effect of various treatments for defect reduction.

Characterization of a New Cleaning Method Using Electrolytic Ionized Water for Polysilicon Chemical Mechanical Polishing Process

In trench isolation technology, the surface layers of poly-Si buried in the trench are contaminated with silica particles and chemical impurities by the conventional chemical-mechanical polishing (CMP) method. These contaminations produce some unexpected patterns and crystal defects in the wafer surface layer after oxidation. Furthermore, it is difficult to remove them by the conventional wet cleaning techniques. In this work, we have established a new post-CMP cleaning method, using electrolytic ionized water containing a small quantity of HCl. The anode water is shown to have a cleaning effect on the metallic and organic contamination, whereas the cathode water is shown to have a removing effect on the particles and an etching effect on the poly-Si surface. We present the optimization results of the post-CMP cleaning condition by investigating the surface-related properties by means of a particle counter, ellipsometry, secondly electron microscopy (SEM), atomic force microscopy (AFM), inductively coupled plasma/mass spectroscopy (ICP/MS), and secondary ion mass spectroscopy (SIMS). Our newly established cleaning method is currently applicable to the actual CMP planarization process for VLSI.

Mechanism of a New Post CMP Cleaning for Trench Isolation Process

CMP has been revealed as an attractive technique to poly Si of trench planalizing process. Major issues of process integration for that purpose have been post-CMP cleaning process. A new post CMP cleaning process which employed special organic surfactant has been reported in this paper. In general, wafers after CMP process are contaminated by particles and metallic impurities in the case of conventional cleaning method. The contamination introduce the defects into the wafers after oxidation. The contamination was removed by new cleaning method. using DI water containing special organic surfactant and silica particles. The experimental work has focused on critical problems that had to be solved, using AFM, EDX and VPDICP/MS.

Development of Dishing-less Slurry for Polysilicon Chemical-Mechanical Polishing Process

Dishing of polysilicon and thinning of the stopper silicon nitride films are crucial problems when the polysilicon embedded by low pressure chemical vapor deposition in the trench and the concavity with respective widths of 0.7 µm and 20–100 µm is simultaneously flattened by chemical-mechanical polishing (CMP). In order to suppress these two occurrences, a high polymer compound mixed slurry was developed and characterized. The pH value of the slurry measured on the polishing abrasive pad was decreased by dilution with de-ionized water, which resulted in cohesion and solidification of the slurry. By using this cohered and solidified slurry when the poly silicon surface is flattened by CMP, the dishing thickness of the polysilicon was suppressed to less than 100 nm at a concavity width of 100 µm. The CMP process using the developed slurry is useful for the advanced trench isolation process and is currently applied to NAND flash memory and high-speed bipolar LSI devices.

Corrosion control technique in copper metallization using gas dissolved water

Copper wiring corrosion occurs after CMP as well as during CMP. It can be reduced by post-CMP cleaning using gas dissolved water. A leakage current between Cu wiring often increases during storage after CMP, which is induced by corrosion. Gas dissolved water is able to not only remove residual impurities but also control the surface potential of Cu and barrier metal. Therefore treatment in gas dissolved water can prevent increasing leakage current.

Modeling on Mechanical Properties of Polishing Pads in CMP Process

Chemical mechanical polishing is an essential process for achieving a high degree of planarization. The planarity after CMP sensitively depends on pattern scales, pattern densities and mechanical properties of polishing pads. In order to simulate the topography after CMP, a numerical model for the polishing pad is proposed. In this model, the surface roughness layer of the polishing pad is assumed as a flat soft layer. The distribution of the contact pressure between the patterned wafer and the polishing pad is calculated with finite element method, and the pattern topography is modified based on the pressure dependency of the polishing rate. The iterations of the contact pressure analyses and the topography modifications give the progress of the polishing process numerically. The model is applied to oxide CMP process with silica slurry and stacked pad of polyurethane and non-woven fabric. The compressive elastic moduli of polyurethane layer and non-woven fabric layer are measured dynamically. The elastic modulus of the soft layer is treated as a fitting parameter between the experimental results and the numerical model. The models with the elastic modulus of 10 MPa for the soft layer show good agreements with the experimental results in both of a short range, where the compressive deformation of the pad is dominant, and a long range, where the bending deformation is dominant. Static measurements for the surface elasticity of the polyurethane layer also give a good agreement with the model. The proposed pad model should be useful for the topography simulation, and it also guides the development of new polishing pads.

Mechanical Planarization Technology. The Current State of Processing and Problems of Chemical-Mechanical Polishing on the Semiconductor Device Manufacturing.

デバイス製造プロセスにCMP法を導入する場合,最も重要なのが安定した加工性能を得るために装置とプロセスをチューニングすることである.例えば,ポリシング特性を決定するパラメータである(1)スラリー,(2)研磨パッド,(3)加工時のウエハ保持方法,(4)研磨パッドの再生方法や条件を最適化することである.また,デバイス製造プロセス上重要となるのがクリーン化である.装置を構成する部材のクリーン化およびCMP後処理方法を確立することでウエハ汚染や他工程の汚染を防ぐことが必要である.またCMPプロセス特有の問題であるスクラッチングやディッシングを防ぐ工夫を行うことが重要である.新しいコンディショナの開発や終点検出用モニタなどのQC装置の開発が急務である.