Naoya Furutake

Chemical Structure Effects of Ring-Type Siloxane Precursors on Properties of Plasma-Polymerized Porous SiOCH Films

Physical and chemical properties of plasma-polymerized SiOCH films were investigated using ring-type siloxane monomers with several kinds of side-chain chemicals, and a design principle of the material and plasma-process was derived to obtain a porous SiOCH film of k < 2.5 with sub-nanometer-scaled porous structure framed by the original ring siloxane backbone. Here, the backbone siloxane structure is fixed as a six-membered Si-O ring of the 0.35 nmΦ, and no progen gas and no post-cure-process were utilized. It was found that unsaturated hydrocarbon side chains such as vinyl increase the deposition rate, and the original monomer structure tends to be kept, reducing the dielectric constant with the porous structure. Large alkyl groups increase the hydrocarbon content in the film as well as the deposition rate. The low radio-frequency power plasma with high precursor concentration also helps the original chemical structure to be preserved. The best solution is to use the ring-type siloxane with both of the vinyl (unsaturated hydrocarbon) and the large alkyl (saturated hydrocarbon) under the low-power plasma condition with the high partial pressure of the precursor. The plasma-polymerized porous SiOCH film is a strong candidate for the low-k film in scale-down 45/32 nm node ultralarge-scaled integrated interconnects featured by the simple and low-cost fabrication processes.

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.

Improving Reliability of Copper Dual-Damascene Interconnects by Impurity Doping and Interface Strengthening

Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability.

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2 /CF4 /O2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Impact of barrier metal sputtering on physical and chemical damages in the low-k SiOCH films is investigated. In RF sputtering system, the potential drop across the anode sheath accelerates the ion in the plasma toward the wafer surface, inducing damages in the low-k SiOCH dielectrics. High DC bias on the target reduces the anode sheath voltage to suppress the process-induced damage in the SiOCH films. For conventional rigid and porous SiOCH films with methyl (–CH3) additives, the accelerated ions break the Si–CH3 bond, pushing up the dielectric constants. A new type of SiOCH film such as a molecular-pore-stacking (MPS) SiOCH, which is consisted of hexagonal silica ring with a large amount of hydrocarbon groups surrounding the core silica structure, exhibits high endurance to the sputtering-induced damages. The long side-chains of the hydrocarbon prevent the direct ion bonberdment to the core Si–CH3 bonds by sacrificing the C–C bond in the chains, keeping the low dielectric constant in the MPS SiOCH.

PZT MIM capacitor with oxygen-doped Ru-electrodes for embedded FeRAM devices

An add-on-type, Pb(Zr,Ti)O/sub 3/ (PZT) metal-insulator- (MIM) capacitor on Al multilevel interconnects is developed for embedded FeRAM devices, concluding that the oxygen-doping into the ruthenium (Ru) electrodes is crucial for obtaining large remnant polarization under a limited process temperature below 450/spl deg/C. The oxygen-doped, Ru bottom-electrode with a granular structure reduces the PZT sputtering temperature below 450/spl deg/C to obtain the ferroelectric perovskite-phase. On the other hand, oxygen doping into the Ru top-electrode suppresses the reductive damage at the interface between the top-electrode and the PZT, keeping the leakage current low. The PZT MIM capacitor with these oxygen-doped, Ru electrodes exhibits the remnant polarization of 21 /spl mu/C/cm/sup 2/ on the Al multilevel interconnects with no degradation of the interconnect reliability, thus applicable to the embedded FeRAM in 0.25 /spl mu/m-CMOS logic LSIs.

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Stress-induced voiding (SIV) is a serious problem in Cu dual-damascene interconnects (DDIs). The stress gradient under vias is the driving force of vacancy diffusion and void generation, therefore stress control in Cu-DDI is an important factor for suppressing SIV. In this study, the stress effect of upper Cu film on SIV in lower Cu lines is investigated, and the stress distribution in Cu-DDI is analyzed by finite element analysis. It is found that SIV in the lower Cu lines is strongly affected not only by the width of lower lines but also by the metallurgical properties of the Cu film in upper metals. Suppression of tensile stress in the via of the upper Cu film decreases the stress gradient in the lower line around the via, and eventually, the driving force of vacancy diffusion to the via bottom. Control of the metallurgical properties to suppress Cu creep during annealing is a key factor for decreasing SIV in lower Cu lines. High-temperature deposition of Cu film with a small coefficient of thermal expansion (CTE) is a solution to suppressing SIV failure in Cu-DDIs.

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter (phi) vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-phi vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

Hybrid-type, Cu dual damascene interconnects (DDI) are fabricated in a porous organosilica film (k = 2.1) inserted between low-k films of hard-mask (HM) and etch-stop (ES) layers. Plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB, k = 2.7) film, instead of SiCN film (k > 4), is selected for these HM and ES layers due to the low k-value as well as the high etch-stop property to the porous film. The line capacitance in the hybrid-type, Cu-DDI with BCB-HM and BCB-ES layers decreases 20% compared with that of the Cu-DDI with SiO/sub 2/-HM and SiCN-ES layers, achieving the effective dielectric constant (k/sub eff/) of 2.6. This new interconnect structure is a strong candidate for the 70 nm-node ULSIs.