Natarajan Mahadeva Iyer

Wafer level high temperature reliability study by backside probing f or a 50um thin TSV wafer

Wafer level reliability of TSV has been studied with respect to FEOL (Front end of line) and BEOL (Back end of line) reliability aspects. TSV keep out zone (KoZ) study has been done with varying gate length and width of transistor. Voltage ramp stress (VRS) analysis has been done by varying gate voltage for different KOZ for both SG and EG oxide devices and found not significant impact to device performance. Testing is done for both thick and thin (50um) wafer and found little effect due to wafer thinning. Wafer level FEOL reliability tests are done at 125 deg C and for a 50um thin wafer, a new methodology by probing the device from back side through TSV with a carrier wafer is demonstrated. Probing of the device from the backside of the device eliminate the thin wafer de-bonding from the carrier wafer and mounting onto a dicing tape. With new methodology reliability of the wafer is improved by eliminating thin wafer debonding and also able to test the thin wafer at higher temperature 125 °C which was not possible with wafer on a dicing tape which can withstand only temperature up to 60°C.

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with poor ideality, mismatch, weak re-surf action and low drain current(Id/μm) of Laterally diffused MOS (LDMOS), degraded RF and 1/f noise of analog CMOS, etc. Innovative solutions which maintain process simplicity and low cost are described in this paper. These new device designs demonstrate excellent performance, such as near perfect-ideality(η)≈1.01 diodes, low leakage, high BV, and BJTs with excellent analog behavior. Fin-based LDMOS and ESD devices outperform conventional planar devices in terms of Id/μm and ESD human body model (HBM) performance, respectively.

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

A DC and pulse stress electro-thermal model that can well describe the dynamic thermal behaviors of most interconnections fabricated in CMOS technology is derived and demonstrated. This model provides for the first time a simple methodology to evaluate the time dependent temperature and resistance of the interconnection under an applied voltage stress, especially critical to E-Fuse development.

Predictive high voltage ESD device design methodology

A - novel predictive design frame work based on physical principles to predict the ESD performance of high voltage device is reported. The device It2 is proportional to the critical current per area of the N+ diffusion resistor or the lightly doped diffusion resistor, both these diffusions constitutes the drain.

ESD Engineering Fully Silicided Large MOSFET Driver for Maximum

Simultaneous optimization of LDD and antipunch-through implant conditions for ESD performance of very large width silicided output driver NMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulsewidth, are detailed.

It\hbox{1}

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.

Performance

A very simple and useful scheme to enhance the ESD performance of the nFinFET is proposed. By incorporating the N-Well (NW) with the nFinFET, it becomes a low holding-voltage SCR if the NW contact is ohmic and becomes a high holding-voltage SCR if the NW contact is a Schottky contact.

Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability

The fundamental physical mechanism decreasing transistor SOA boundary and ID with the increasing transistor total width is identified and reported for the first time. The skin effect, proximity and Hall-effect arising from the large varying-current are attributed to transistor SOA degradation.

Enhanced nFinFET ESD performance

An abnormal I/O failure caused by the board-capacitor (BC) of the HBM tester is reported. Without any discharge component, the BC was charged up to the high voltage during the HBM test of the No-Connect pin. As the relay switches to the next pin to do the DC I-V curve trace or subsequent HBM zapping, the BC releases its stored charges to become a MM-Like ESD event of the I/O pin.

Physics of SOA degradation phenomena in power transistors under ESD conditions

A novel diode structure is successfully designed for the first time to protect the power line against the ESD stress condition in the high voltage (HV) CMOS technology nodes. Controlled by the voltage difference between VDD and signal, the depletion regions of two HV-NWs can shut off or turn on the current path to the ground (GND) of the diode depending on whether it is under normal operation mode or ESD event.