Manjunatha Prabhu

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

A DC and pulse stress electro-thermal model that can well describe the dynamic thermal behaviors of most interconnections fabricated in CMOS technology is derived and demonstrated. This model provides for the first time a simple methodology to evaluate the time dependent temperature and resistance of the interconnection under an applied voltage stress, especially critical to E-Fuse development.

Predictive high voltage ESD device design methodology

A - novel predictive design frame work based on physical principles to predict the ESD performance of high voltage device is reported. The device It2 is proportional to the critical current per area of the N+ diffusion resistor or the lightly doped diffusion resistor, both these diffusions constitutes the drain.

Methodology to achieve planar technology-like ESD performance in FINFET process

Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.

Impact of TSV process on 14nm FEOL and BEOL reliability

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

Enhanced nFinFET ESD performance

A very simple and useful scheme to enhance the ESD performance of the nFinFET is proposed. By incorporating the N-Well (NW) with the nFinFET, it becomes a low holding-voltage SCR if the NW contact is ohmic and becomes a high holding-voltage SCR if the NW contact is a Schottky contact.

Physics of SOA degradation phenomena in power transistors under ESD conditions

The fundamental physical mechanism decreasing transistor SOA boundary and ID with the increasing transistor total width is identified and reported for the first time. The skin effect, proximity and Hall-effect arising from the large varying-current are attributed to transistor SOA degradation.

Source of miscorrelation of product level HBM to TLP test results

Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition which is worse at low current compared to high ESD current. Such results cannot be replicated in TLP.

New voltage controlled diode for power rail and regulator ESD protection

A novel diode structure is successfully designed for the first time to protect the power line against the ESD stress condition in the high voltage (HV) CMOS technology nodes. Controlled by the voltage difference between VDD and signal, the depletion regions of two HV-NWs can shut off or turn on the current path to the ground (GND) of the diode depending on whether it is under normal operation mode or ESD event.

ESD Robust Fully Salicided 5-V Integrated Power MOSFET in Submicron CMOS

A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast resistor. This scheme builds the ballast resistors on the top of the source and drain, without any increase in silicon footprint unlike prior methods, while maintaining standard transistor parametric performance.

Printed-circuit board (PCB) charge induced product yield-loss during the final test

The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that the voltage is high enough to damage the components of the low voltage circuits (1.8V), but is still too low to turn on the ESD protection device.