Ruchil Jain

Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

Predictive high voltage ESD device design methodology

A - novel predictive design frame work based on physical principles to predict the ESD performance of high voltage device is reported. The device It2 is proportional to the critical current per area of the N+ diffusion resistor or the lightly doped diffusion resistor, both these diffusions constitutes the drain.

A Solution Toward the OFF-State Degradation in Drain-Extended MOS Device

We investigated the surface band-to-band tunnelling (BTBT) current under the off-state condition in drain-extended MOS (DeMOS) devices. We found significant gate-induced drain leakage current due to surface BTBT, which was also reported earlier as the dominant cause of early time-dependent dielectric breakdown and device failure. Furthermore, a layout solution for the existing DeMOS device is proposed in order to mitigate the surface BTBT current and the associated gate oxide reliability issues, without sacrificing the mixed-signal performance of the device.

Source of miscorrelation of product level HBM to TLP test results

Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition which is worse at low current compared to high ESD current. Such results cannot be replicated in TLP.

A novel contact field plate application in drain-extended-MOSFET transistors

A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate can improve the device robustness in terms of hot carrier injection.

Effect of contact field plate on hot-carrier-induced on-resistance degradation in n-Drain extended MOS transistors

In this paper, various kinds of n-Drain Extended MOS with contact field plate are investigated. Improved on-resistance degradation is observed for all the kinds of contact field plates. Technology Computer-Aided-Design simulation reveals that the impact ionization rate in the drift region is decreased for all kinds of contact field plates.

New voltage controlled diode for power rail and regulator ESD protection

A novel diode structure is successfully designed for the first time to protect the power line against the ESD stress condition in the high voltage (HV) CMOS technology nodes. Controlled by the voltage difference between VDD and signal, the depletion regions of two HV-NWs can shut off or turn on the current path to the ground (GND) of the diode depending on whether it is under normal operation mode or ESD event.