Yohann Luque

A 65 nm CMOS - Stacked Folded Fully Differential (SFFD) PA structure for W-CDMA application

This paper presents a 65 nm CMOS-power amplifier (PA) designed for mobile communications.The PA is based on a new structure, the stacked folded fully differential (SFFD) which is inspired by a push-pull structure. The PA is designed for the UMTS W-CDMA standard which requires linearity from -20 dBm to 24 dBm output power. The power amplifier provides 31 dBm output power with 26% of power added efficiency (PAE) at 1.95 GHz. The linear gain is 20 dB and the compression point (OCP1) is 25.6 dBm. In order to meet the UMTS W-CDMA requirements, the PA is linear until 24 dBm, which is the maximum output power required by this standard.

Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1 60GHz power amplifier using 65nm CMOS technology

Millimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1-4 splitter have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation is based on a thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors in 65 nm CMOS technology from STMicroelectronics. A lumped model based analysis is presented to compare pure voltage and mixed voltage and current combining techniques. Simulated and measured results are reported. At 61 GHz, the PA achieves a peak power gain of 20 dB with a 13.5 dBm 1dB-output compression point (OCP1dB), 15.6 dBm output power and a Power Added Efficiency (PAE) of 6.6% from a 1.2 V supply. To the authors knowledge, these results represent the highest linear output power and gain performances among PAs using the same technology.

Design of a fully integrated CMOS self-testable RF power amplifier using a thermal sensor

This paper presents a wideband RF power amplifier (PA) dedicated to 2GHz applications integrating a contact-less temperature sensor that allows on-chip observation and testing of the PA. Indeed, based on the static and dynamic local temperature changes caused by the PA operation, the thermal sensor can sense parameters such as output power or efficiency. This principle is applied to a 65nm CMOS PA with an OCP1 of 21dBm. We demonstrate that the output voltage of the thermal sensor follows the PA efficiency under single tone and multi-tone input signal conditions.

CMOS SFFDS PA with coupled transformer for high power RF applications

This paper presents a 65nm CMOS power amplifier (PA) using a coupled transformer. The PA is based on an original structure, called Stacked Folded Fully Differential Structure (SFFDS). It is applied to the UMTS W-CDMA standard. The parallel SFFDS power amplifier provides 30.5 dBm of output power with 20% of power added efficiency (PAE) at 1.95 GHz. The output compression point (OCP1) is 27.5 dBm and the PA is linear up to 24 dBm in order to meet the maximum output power required by the UMTS W-CDMA standard.

A 0.13 μm CMOS stacked folded fully differential PA structure for W-CDMA Application

This paper describes the feasibility of a power amplifier (PA) in 0.13mum CMOS technology from STMicroelectronics. It is designed for the UMTS W-CDMA standard. This power amplifier provides 33 dBm maximal output power with 60% of power added efficiency (PAE) at 1.95 GHz. This standard requires linearity from -20 dBm till 24 dBm output power. The linear gain is 16.7 dB and the compression point (OCP1) is 28.25 dBm. In order to fulfil UMTS W-CDMA specifications, especially on linearity, the maximum 24dBm of output power required are reached in a linear class of operation.

A fully integrated 65 nm CMOS cascode HSFDS PA dedicated to 802.11n application

This paper presents a 65nm CMOS-power amplifier (PA) designed for WiFi communications. The PA is based on a Half Stacked Folded Differential Structure (HSFDS) cascoded. The PA is designed for the WiFi 802.11n standard. The power amplifier provides 24.5 dBm output powers with 25% of power added efficiency (PAE) at 2.45 GHz. The linear gain is 15.5 dB and the compression point (OCP1) is 18.5 dBm. In order to meet the 802.11n requirements, the PA is linear until 16 dBm, which is the maximum output power required by this standard.

A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA application

This paper presents a 65nm CMOS-Power Amplifier (PA) designed for UMTS standard. It is based on a triple Stacked Folded pseudo-Differential Structure (triple SFDS) power stage and a differential cascode driver stage. The PA provides 31.5 dBm maximal output power (Pmax) with 20% of maximal power added efficiency (PAEmax) at 1.95 GHz. The linear gain is 37 dB and the compression point (OCP1) is 29.5 dBm. In order to fulfill the W-CDMA requirements, the PA respects the ACLR requirements until 23 dBm.