Nathalie Labat

Evidence of traps creation in GaN/AlGaN/GaN HEMTs after a 3000 hour on-state and off-state hot-electron stress

A long-term 3000-hour test under on-state conditions (VDS =25V, 6W/mm constant dissipated power) and off-state conditions (V DS=46V, VGS=-6V) on GaN/AlGaN/GaN HEMTs is presented. Trapping presence and hot-electrons effect are characterized by means of low-frequency techniques (low-frequency noise measurements, transconductance frequency dispersion, gate-lag). The on-state stress shows the most important degradation. Since our measurements point out to the creation of traps in the gate-to-drain surface region during the stress, this degradation is ascribed to the effect of hot-electrons

Kink effect in HEMT structures: A trap-related semi-quantitative model and an empirical approach for spice simulation

Abstract The mechanism of kink effect in AlGaAs/GaAs high-electron-mobility transistors (conventional, normally-on) is reported. An analytical model, in good agreement with experimental results (behaviour of the kink voltage with temperature and gate voltage) shows that this effect is related to impact ionization phenomenon. Accurate prediction of the I − V characteristics including the kink effect can be carried out, extending the d.c.-equations of the SPICE GaAs-FET model. Three parameters are used in the kink region for the drain current. All of them are extracted from experimentally measured I − V characteristics and preserve physical meaning.

Characterization and analysis of trap-related effects in AlGaN-GaN HEMTs

Abstract Traps are characterized in AlGaN–GaN HEMTs by means of DLTS techniques and the associated charge/discharge behavior is interpreted with the aid of numerical device simulations. Under specific bias conditions, buffer traps can produce “false” surface-trap signals, i.e. the same type of current-mode DLTS (I-DLTS) or ICTS signals that are generally attributed to surface traps. Clarifying this aspect is important for both reliability testing and device optimization, as it can lead to erroneous identification of the degradation mechanism, thus resulting in wrong correction actions on the technological process.

AlGaN/GaN HEMT Reliability Assessment by means of Low Frequency Noise Measurements

Although impressive results have been published for GaN-based transistors in a large frequency range reliability demonstration is becoming an important subject of concern. In this article the conditions of a long term DC life test is presented and a detailed description of pre- and post-test characterization by means of Low Frequency Noise measurements (LFN) is discussed. The transistor parameters (IDSS, Ron, Vp) and the drain noise spectra presented an evolution strictly related to the biasing point during the stress. This demonstrates that LFN measurement is a useful tool to investigate degradation in GaN HEMTs.

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

The reliability of InP/GaAsSb/InP DHBTs designed for very high-speed ICs applications is studied after storage accelerated aging tests performed up to 2000 hours at ambient temperatures of 180, 210 and 240°C. The HiCuM model was used for modelling DC electrical characteristics measured during aging tests. The signature of the major degradation mechanism points out an evolution of the emitter access resistance. The failure mechanism is related to the Au and/or Ti diffusion into InGaAs emitter contact layer. However, the maximum current gain decrease is lower than 7 % after 2000 hours at 240°C. This shows the robustness of the InP/GaAsSb/InP DHBT under test.

Analysis of current collapse effect in AlGaN/GaN HEMT: Experiments and numerical simulations

In this work, current collapse effects in AlGaN/GaN HEMTs are investigated by means of measurements and two-dimensional physical simulations. According to pulsed measurements, the used devices exhibit a significant gate-lag and a less pronounced drain-lag ascribed to the presence of surface/barrier and buffer traps, respectively. As a matter of fact, two trap levels (0.45 eV and 0.78 eV) were extracted by trapping analysis based on isothermal current transient. On the other hand, 2D physical simulations suggest that the kink effect can be explained by electron trapping into barrier traps and a consequent electron emission after a certain electric-field is reached.

Analysis of Schottky Gate degradation evolution in AlGaN/GaN HEMTs during HTRB stress

GaN based technologies are promising in terms of electrical performances for power and high frequencies applications and their reliability assessment remains a burning issue. Thus, a good understanding of their degradation mechanisms is required to warranty their reliability. In this paper, an electrical parasitic effect has been observed on the gate-source diode forward characteristics of a set of devices under HTRB stress carried out at 175 °C up to 4000 h. This parasitic effect has been attributed to lateral surface conduction and correlated with EL signature under diode forward biasing conditions but not under transistor pinch-off biasing conditions. Then, physical analyses have pointed out the formation and growing over time of pits and cracks at the gate edge on the drain side

Link between low frequency noise and reliability of compound semiconductor HEMTs and HBTs

On the basis of papers published on the fundamental and excess LF noise sources in compound semiconductor transistors, two main issues are addressed in this paper: i) the characterization of LF noise sources linked to parasitic effects induced by innovative component architecture in emerging technologies such as GaN-based HEMTs and GaAsSb HBTs. ii) the identification of LF noise sources linked to degradation mechanisms in compound semiconductor devices issued from mature technologies. Examples of experimental correlation between LF noise and parasitic effects (i.e. potential electrical performance penalization) or failure mechanisms in III-V HEMTs and HBTs are described with data related to recent technological developments.

Induced damages on CMOS and bipolar integrated structures under focused ion beam irradiation

Focused ion beam used for failure analysis or repairing of ASICs degrades device performances by charging up the surface circuit. The influence of focused ion beam on device electrical performances has been studied to understand the behavior of basic test integrated circuits. We have performed measurements on test structures : MOS capacitors and transistors and bipolar transistors. Oxide trap filling and leakage current through the structures induce different failure mechanisms such as : threshold voltage shift in MOS transistors, deep depletion state in MOS capacitors and current gain decrease in bipolar transistors. A characterization of these effects and a first interpretation are proposed.

Analysis of hot electron degradations in pseudomorphic HEMTs by DCTS and LF noise characterization

Abstract Commercial pseudomorphic AlGaAs InGaAs HEMTs designed for low noise operation have demonstrated weak sensitivity to hot electron stress. We have investigated underlying physical mechanisms by LF channel noise analysis and Drain Current Transient Spectroscopy (DCTS). A link has been established between the enhancement due to hot electron stress of the hole current collected by the gate and the modulation of electron trap effective density located beneath the gate.