Brice Grandchamp

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

The reliability of InP/GaAsSb/InP DHBTs designed for very high-speed ICs applications is studied after storage accelerated aging tests performed up to 2000 hours at ambient temperatures of 180, 210 and 240°C. The HiCuM model was used for modelling DC electrical characteristics measured during aging tests. The signature of the major degradation mechanism points out an evolution of the emitter access resistance. The failure mechanism is related to the Au and/or Ti diffusion into InGaAs emitter contact layer. However, the maximum current gain decrease is lower than 7 % after 2000 hours at 240°C. This shows the robustness of the InP/GaAsSb/InP DHBT under test.

Characterization and Modeling of Graphene Transistor Low-Frequency Noise

This brief presents low-frequency noise measurements on a graphene field-effect transistor with graphene layer decomposed from SiC substrate. The measurements indicate the predominance of flicker noise in the current noise source measured between drain and source with quadratic dependence with a drain current. The noise level is inversely proportional to the channel area indicating the location of the main noise source to be in graphene layer. From these measurements, the main noise sources, including the main flicker noise and the Johnson noise contributions, have been introduced in a compact model. This compact model has been built using dc characterization results. Finally, the noise compact model has been validated through comparison to noise measurement.

Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management

More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

Abstract The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.

Advancements on reliability-aware analog circuit design

This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature stress it suffers which results in (slowly) varying model parameters over time. Due to its straightforward implementation in commercial Computer Aided Design (CAD) flows, this method allows designers creating reliability-aware circuit architectures at an early stage of the design procedure, well before real circuits are actually fabricated. Application examples and results are presented for an InP/InGaAs DHBT process, but the universality of the method makes it suitable also for silicon based technologies such as CMOS and (SiGe) BiCMOS.

Thermal aging model of InP/InGaAs/InP DHBT

Abstract This paper presents the measurement result and modeling of the storage accelerated aging tests performed on InP/InGaAs/InP DHBT. From the Gummel characteristics, we observe that the principle mode of device degradation results from the increase of base current and reduction in the current gain which comes from the base–emitter junction periphery. Topics covered include: (1) underlying physical mechanism of base current degradation; (2) choosing HICUM model LEVEL2 for the modeling purpose; (3) evolution of model parameters with stress time after the extraction of model parameter before aging and the description of the parameter drift with suitable equation; (4) implementation in compact electrical model allows to simulate the impact of device failure mechanisms on the circuit in operating conditions.

Link between low frequency noise and reliability of compound semiconductor HEMTs and HBTs

On the basis of papers published on the fundamental and excess LF noise sources in compound semiconductor transistors, two main issues are addressed in this paper: i) the characterization of LF noise sources linked to parasitic effects induced by innovative component architecture in emerging technologies such as GaN-based HEMTs and GaAsSb HBTs. ii) the identification of LF noise sources linked to degradation mechanisms in compound semiconductor devices issued from mature technologies. Examples of experimental correlation between LF noise and parasitic effects (i.e. potential electrical performance penalization) or failure mechanisms in III-V HEMTs and HBTs are described with data related to recent technological developments.

InP HBT Thermal Management by Transferring to High Thermal Conductivity Silicon Substrate

We report about the self-heating management of an InP double heterojunction bipolar transistor (DHBT) by the way of the thermal resistance. In order to reduce this latter, an AlInP/GaAsSb DHBT has been transferred on a silicon substrate offering a high thermal conductivity. According to our thermal resistance measurements on a 0.8 × 6 μm2 DHBT, a low thermal resistance of 1625 K/W is obtained, 65 % lower than for the same device fabricated on its own substrate of InP and which exhibited a value of 4452 K/W.

Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements

We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87°C to 240°C, collector current density fixed at 400 kA/cm2, and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance RTH and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.

Evidence of RTS noise in emitter-base periphery of InP/GaAsSb/InP HBT

This paper presents low frequency noise (LF) measurements on InP/GaAsSb/InP HBTs. The spectral analysis of the dominant base noise source SIb has allowed to identify the 1/f noise and a RTS noise component. From LF noise measurements as a function of the temperature, the parameters of the traps responsible for the RTS noise signature have been extracted. An activation energy close to 200 eV with a capture cross-section near 1times10-18 cm2 have been determined.