Nathan J. Conrad

Black Phosphorus–Monolayer MoS2 van der Waals Heterojunction p–n Diode

Phosphorene, a elemental 2D material, which is the monolayer of black phosphorus, has been mechanically exfoliated recently. In its bulk form, black phosphorus shows high carrier mobility (∼10,000 cm(2)/V·s) and a ∼0.3 eV direct band gap. Well-behaved p-type field-effect transistors with mobilities of up to 1000 cm(2)/V·s, as well as phototransistors, have been demonstrated on few-layer black phosphorus, showing its promise for electronics and optoelectronics applications due to its high hole mobility and thickness-dependent direct band gap. However, p–n junctions, the basic building blocks of modern electronic and optoelectronic devices, have not yet been realized based on black phosphorus. In this paper, we demonstrate a gate-tunable p–n diode based on a p-type black phosphorus/n-type monolayer MoS2 van der Waals p–n heterojunction. Upon illumination, these ultrathin p–n diodes show a maximum photodetection responsivity of 418 mA/W at the wavelength of 633 nm and photovoltaic energy conversion with an external quantum efficiency of 0.3%. These p–n diodes show promise for broad-band photodetection and solar energy harvesting.

First experimental demonstration of Ge CMOS circuits

We report the first experimental demonstration of Ge CMOS circuits, based on a novel recessed channel and S/D technique. Aggressively scaled non-Si CMOS logic devices with channel lengths (Lch) from 500 to 20 nm, channel thicknesses (Tch) of 25 and 15 nm, EOTs of 4.5 and 3 nm and a small width ratio (Wn:Wp=1.2) are realized on a Ge-on-insulator (GeOI) substrate. The CMOS inverters have high voltage gain of up to 36 V/V, which is the best value among all of the non-Si CMOS results by the standard top-down approach. Scalability studies on Ge CMOS inverters down to 20 nm are carried out for the first time. NAND and NOR logic gates are also investigated.

Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., ION, IOFF, Vth, SS, RC) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔVth, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.

Steep-slope hysteresis-free negative capacitance MoS 2 transistors

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal–oxide–semiconductor field-effect transistor (MOSFET) at 60 mV dec−1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4–12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm−1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.A field-effect MoS2 transistor with a negative capacitor in its gate shows stable, hysteresis-free performance characterized by a sub-thermionic sub-threshold slope.

High-Performance InAlN/GaN MOSHEMTs Enabled by Atomic Layer Epitaxy MgCaO as Gate Dielectric

We have demonstrated high-performance InAlN/ GaN MOS high-electron-mobility-transistors (MOSHEMTs) with various channel lengths (L_ch) of 85-250 nm using atomic-layer-epitaxy (ALE) crystalline Mg_0.25Ca_0.75O as gate dielectric. With a nearly lattice matched epitaxial oxide, the interface between oxide and barrier is improved. The gate leakage current of MOSHEMT is reduced by six orders of magnitude compared with HEMT. An OFF-state leakage current of 3 × 10^-13 A/mm, ON/OFF ratio of 4 × 10¹², almost ideal subthreshold swing of 62 mV/decade, low drain current noise with Hooge parameter of 10^-4, and negligible current collapse and hysteresis are realized. The 85-nm Lch MOSHEMT also exhibits good ON-state performance with I_dmax = 2.25 A/mm, R_ON = 1.3 Ω · mm, and g_max = 475 mS/mm, showing that ALE MgCaO is a promising gate dielectric for GaN device applications.

Towards high-performance two-dimensional black phosphorus optoelectronic devices: the role of metal contacts

The metal contacts on 2D black phosphorus field-effect transistor and photodetectors are studied. The metal work functions can significantly impact the Schottky barrier at the metal-semiconductor contact in black phosphorus devices. Higher metal work functions lead to larger output hole currents in p-type transistors, while ambipolar characteristics can be observed with lower work function metals. Photodetectors with record high photoresponsivity (223 mA/W) are demonstrated on black phosphorus through contact-engineering.

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.

Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs

Furthering Si CMOS scaling requires development of high-mobility channel materials and advanced device structures to improve the electrostatic control. We demonstrate the fabrication of gate-all-around (GAA) indium gallium arsenide (InGaAs) MOSFETs with highly scaled atomic-layer-deposited gate dielectrics. InGaAs, with its high electron mobility, allows higher drive currents and other on-state performance compared to silicon. The GAA structure provides superior electrostatic control of the MOSFET channel with outstanding off-state performance. A subthreshold slope of 72 mV/dec, electron mobility of 764 cm2/V·s, and an on-current of 1.59 mA/μm are demonstrated, for example. Variability studies on on-state and off-state performances caused by the number of nanowire channels are also presented.

Low-frequency noise and RTN on near-ballistic III–V GAA nanowire MOSFETs

In this work, we report the first observation of RTN in highly scaled InGaAs GAA MOSFETs fabricated by a top-down approach. RTN and low frequency noise were systematically studied for devices with various gate dielectrics, channel lengths and nanowire diameters. Mobility fluctuation is confirmed to be the source of low-frequency noise, showing 1/f characteristics. Low-frequency noise was found to decrease as the channel length scaled down from 80 nm to 20 nm, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET.

Demonstration of Ge CMOS inverter and ring oscillator with 10 nm ultra-thin channel

In conclusion, we have demonstrated Ge CMOS devices with further scaled channel thickness of 10 nm. 9-stage ring oscillators are successfully realized. The channel thickness dependences of the devices behaviors are also studied and smaller Tch provides reduced SS and DIBL of MOSFETs and better voltage gain of CMOS inverters.