SangHoon Shin

Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., ION, IOFF, Vth, SS, RC) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔVth, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.

Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target

3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature

I_{\mathrm{{\scriptscriptstyle ON}}}

Origin and implications of hot carrier degradation of Gate-all-around nanowire III–V MOSFETs

, along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs.

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, AT(x, y, z; t), at the NW level is important for predicting activity-induced variability within an IC, as well as characterization of various reliability issues, such as, NBTI, PBTI, HCI, and TDDB that depend sensitively on self-heating. In this paper, a 3-D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in GAA devices. Our results identify complex heat dissipation pathways characterized by multiple time constants. First, the nanowires heat up quickly (τGAA-NW ~ nSec), then heat spreads all over the gate contact pad (τG-pad ~ 100 nSec), and finally, the heat exits through the heat sink at the bottom of the substrate (τsub ~ mSec). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices.

Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs

Although ultra-scaled III-V Gate-all-around (GAA) nanowire (NW) MOSFETs have been studied for their immunity to short channel effects, the degradation mechanisms, such as, hot carrier injection (HCI) in the NW MOSFETs are yet to be studied systematically. In this paper, we examine how HCI affects the NW device performance (ΔVth, ΔSS in both stress and recovery) at different bias conditions, and demonstrate that, unlike positive bias temperature instability (PBTI) in NMOS transistors, the HCI degradation is dominated by charge trapping. We analyze the implications of spatial charge trapping on device performance through experiments and simulation. We find that the distinctive features of HCI degradation of GAA NWs structure can be consistently interpreted by a Sentaurus™-based TCAD simulation.

Low-frequency noise and RTN on near-ballistic III–V GAA nanowire MOSFETs

In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.

Characterization of self-heating leads to universal scaling of HCI degradation of multi-fin SOI FinFETs

Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.

Substrate and layout engineering to suppress self-heating in floating body transistors

In this work, we report the first observation of RTN in highly scaled InGaAs GAA MOSFETs fabricated by a top-down approach. RTN and low frequency noise were systematically studied for devices with various gate dielectrics, channel lengths and nanowire diameters. Mobility fluctuation is confirmed to be the source of low-frequency noise, showing 1/f characteristics. Low-frequency noise was found to decrease as the channel length scaled down from 80 nm to 20 nm, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET.

A novel synthesis of Rent's rule and effective-media theory predicts FEOL and BEOL reliability of self-heated ICs

SOI FinFETs and other Gate-all-around (GAA) transistors topologies have excellent 3-D electrostatic control and therefore, have been suggested as potential technology options for sub-14 nm technology nodes. Unfortunately, the narrow gate geometry and reduced gate pitch suppress heat dissipation and increase thermal cross-talk, leading to severe self-heating of these transistors. Self-heating degrades performance and makes the classical reliability theories based on T_L~T_sub irrelevant. In this paper, first, we propose a physics-based thermal circuit compact model for multi-fin SOI FinFETs to characterize self-heating and validate the results by AC conductance method. Next, we analyze HCI degradation varying with the number of fin (N_fin), chuck temperature (T_sub) and AC frequency (f). The results show that HCI degradation dependent variables (N_FIN, T_sub, f) can be correlated to the lattice temperature (T_L = g(N_FIN, T_sub, f)) and obey the universal degradation curve (ΔV_th(T_L) = f(S(T_L) × t)). Si-O bond-dispersion model explains the universal curve; therefore, the model can be used for a long term reliability projection with arbitrary combination N_fin, T_sub, f, etc.